An Efficient Approach to Manage DMA Descriptors and Evaluate PCIe-Based DMA Performance for ALICE Common Readout Unit (CRU)

Abstract

This paper presents the status of performance evaluation of Peripheral Component Interconnect (PCIe)-based Direct Memory Access (DMA) engine for A Large Ion Collider Experiment-Common Readout Unit (ALICE-CRU) upgrade program using advanced Intel Arria 10 FPGA. The CRU will mainly read out most of the upgraded sub-detectors data and transport the same through the PCIe-DMA engine to server. DMA engine moves data using descriptor. DMA controller pushes those descriptors toward DMA engine. The main goal of this paper is to explain the way DMA engine is to be controlled by DMA controller such that max DMA performance can be achieved. The DMA performance has been evaluated on various server grade machines using Intel Arria 10 FPGA kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html, [1]). The result is around 95% of theoretical DMA engine bandwidth.