The SARC Architecture

Alex Ramirez,Gerogi Gaydadjiev,Friman Sanchez,Sebastian Isaza,Catalin Ciobanu,Mauricio Alvarez Mesa,Ben Juurlink,Felipe Cabarcas,Arnaldo Azevedo,Cor Meenderinck

doi:10.1109/mm.2010.79

The SARC Architecture

Alex Ramirez, Gerogi Gaydadjiev + Show 8 more

https://doi.org/10.1109/mm.2010.79

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Journal: IEEE micro	Publication Date: Sep 1, 2010
Citations: 48

Affiliation: Universitat Politècnica de Catalunya, Technische Universität Berlin, Barcelona Supercomputing Center, Delft University of Technology

#Direct Memory Access Engines #Direct Memory Access + Show 8 more

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Abstract

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.

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