Direct Etching Research Articles

Sculpting In‐plane Fractal Porous Patterns in Two‐Dimensional MOF Nanocrystals for Photoelectrocatalytic CO2 Reduction

AbstractHerein, by choosing few‐nm‐thin two‐dimensional (2D) nanocrystals of MOF‐5 containing in‐planner square lattices as a modular platform, a crystal lattice‐guided wet‐chemical etching has been rationally accomplished. As a result, two attractive pore patterns carrying Euclidean curvatures; precisely, plus(+)‐shaped and fractal‐patterned pores via ⟨100⟩ and ⟨110⟩ directional etching, respectively, are regulated in contrast to habitually formed spherical‐shaped random etches on MOF surface. In agreement with the theoretical calculations, a diffusion‐limited etching process has been optimized to devise high‐yield of size‐tunable fractal‐pores on the MOF surface that tenders for a compatibly high payload of catalytic ReI‐complexes using the existing large edge area once modified into a free amine‐group‐exposed inner pore surface. Finally, on benefiting from the long‐range fractal opening in 2D MOF support structure, while loaded on an electrode surface, a facilitated cross‐interface charge‐transportation and well‐exposure of immobilized ReI‐catalysts are anticipated, thus realizing enhanced activity and stability of the supported catalyst in photoelectrochemical CO2‐to‐CO reduction.

An Ultra‐Thin, Ultra‐High Capacitance Density Tantalum Capacitor for 3D Packaging

AbstractAlthough embedded capacitors have been applied and researched for many years, their large‐scale application still faces challenges such as low capacitance density, high thickness, high cost, and incompatibility with integrated processes. In this work, a breakthrough has been made in the fabrication of ultra‐thin tantalum (Ta) capacitors with ultra‐high capacitance density that can be used for 3D packaging. The key to these excellent performances is the application of Ta foil with nano‐porous structure to the anode of the capacitor. The Ta foil with high specific surface area (SSA) is successfully prepared by direct current pulse etching. At a current density of 15 mA cm−2, a pulse frequency of 50 Hz, and a duty cycle of 30%, the SSA of Ta foil is increased by 76 times after etching in an electrolyte with 0.01 v% TOA for 30 min. Based on this, Ta capacitors with a form factor of less than 40 µm, showing a capacitance density of 750 nF mm−2 and a leakage current of less than 2.1 × 10−7 A at 8 V is successfully fabricated. To the best of the authors’ knowledge, this is the highest capacitance density reported to date for the mentioned form factors.

Integrated photonics on the dielectrically loaded lithium niobate on insulator platform

Thin-film lithium niobate on insulator (LNOI) is emerging as one of the promising platforms for integrated photonics due to the excellent material properties of lithium niobate, which includes a strong electro-optic effect, high second-order optical nonlinearity, a large optical transparency window, and low material loss. Although direct etching of lithium niobate has been adopted more widely in recent years, it remains to be seen if it will be adopted in foundry processes due to the incompatibility with standard CMOS fabrication processes. Thus, the scalability of the LNOI platform is currently still limited when compared with other platforms such as silicon photonics. Dielectrically loaded LNOI waveguides may present an alternative. These waveguides have been used to demonstrate a range of optical components with a simplified fabrication process while demonstrating competitive performance. In this contribution, we review the recent progress in dielectrically loaded LNOI waveguides, summarize the advantages and disadvantages of different loading materials, compare the performance of different platforms, and discuss the future of these platforms for photonic integrated circuits.

Design and Fabrication of PTFE Substrate-Integrated Waveguide Butler Matrix for Short Millimeter Waves

We attempt to design and fabricate of a 4×4 Butler matrix for short-millimeter-wave frequencies by using the microfabrication process for a polytetrafluoroethylene (PTFE) substrate-integrated waveguide (SIW) by the synchrotron radiation (SR) direct etching of PTFE and the addition of a metal film by sputter deposition. First, the dimensions of the PTFE SIW using rectangular through-holes for G-band (140-220 GHz) operation are determined, and a cruciform 90 ° hybrid coupler and an intersection circuit are connected by the PTFE SIW to design the Butler matrix. Then, a trial fabrication is performed. Finally, the validity of the design result and the fabrication process is verified by measuring the radiation pattern.

3D-crumpled graphitic carbon nitride achieving promoted visible-light-driven molecular oxygen activation for phenol degradation

Boosting optical absorption and charge transfer of g-C3N4 is of great importance but a challenging task for developing metal-free high-performance photocatalyst. Herein, 3D-crumpled g-C3N4 (DCN) is synthesized through a direct top-down thermal etching strategy. The thermal exfoliation of layered bulk g-C3N4 (BCN) in air atmosphere induces partial distortion of heptazine-based g-C3N4 nanosheet, which further self-assemble into 3D-crumpled network structure. Spectroscopic and photoelectrochemical characterization demonstrate that the unique DCN can not only remarkably extend the visible-light response region to 600 nm by awakening the n-π* electron transition, but also significantly promote O2 activation for selective H2O2 generation owing to the intensified electron delocalization and charge transport ability. Thus, DCN catalyst realizes an excellent photocatalytic phenol degradation rate under visible light irradiation (0.690 h−1), far (4.4-fold) out from the BCN counterparts. This work enables synergistic optimization of optical absorption, charge transport and surface-active sites by constructing a 3D-crumpled structure, which expands the engineering toolbox of metal-free skeleton photocatalyst for developing practical and economical catalysts for environmental remediation.

ZIF-derived non-bonding Co/Zn coordinated hollow carbon nitride for enhanced removal of antibiotic contaminants by peroxymonosulfate activation: Performance and mechanism

Co–Zn–N–C catalyst (MCZC) with neighboring Co and Zn pairs anchored on hollow carbon nitride was constructed by the direct etching of zeolitic imidazolate frameworks assembled with Co and Zn. Adequate characterizations and density functional theory (DFT) studies confirmed the successful construction of non-bonding Co and Zn pairs with enhanced electron transfer on Co sites by adjacent Zn sites. Based on the synergy of adjacent Co and Zn atom pairs, the MCZC/Perxymosulfate (PMS) system achieved 99.6% Tetracycline (TC) degradation in 24 min with a mineralization rate of 55.8% and PMS decomposition efficiency of 73.1%. DFT calculation based on the Fukui index identified the sites susceptible to attack by the active species. TC degradation pathways could be inferred, and reduced toxicity of intermediates was observed. This work provides new insights into the design of MOF-derived bimetallic catalysts and the importance of the interaction between adjacent metal active sites to catalytic performance.

Optimization of the Formations Parameters of Hollow Channels in Glass by Direct Laser Writing and Selective Etching

Optimization of the Formations Parameters of Hollow Channels in Glass by Direct Laser Writing and Selective Etching

Morphological and structural characteristics of Gallium Nitride (GaN) porosity using image processing

Attaining a generalized porosity measurement based on the conventional measuring methods is unfeasible due to thin and complex layers on Gallium Nitride (GaN) film. Therefore, there is an impetus for developing a method of estimating general fabric porosity via image processing techniques. This study is aimed to investigate and validate a new technique for extracting the GaN porosity in terms of morphological and structural characteristics using an image processing technique. The anodization on porous GaN films is prepared by using direct current photo-assisted electrochemical etching (DC-PECE) etching technique. The quantitative structural characteristics based on mathematical morphology is analyzed using Field Emission Scanning Electron Microscopy (FESEM) and Atomic Force Microscopy (AFM). To validate the method, the evaluation of porous GaN quality is performed through a non-destructive investigation of its nanostructures using adapting image analysis techniques. Porosity of the structures obtained by calculating the areas occupied by the pores. The quantitative results were obtained and showing good agreement between two modes of measurement and calculation (percentage porosity and pore depth) based on the image-processing data with 91 % and 78 % correlation coefficient.

New insight into anodization of aluminium with focused ion beam pre-patterning

The self-ordered anodic aluminium oxide (AAO) structure consists of micron-scale domains—defect-free areas with a hexagonal arrangement of pores. A substantial increase in domain size is possible solely by pre-patterning the aluminium surface in the form of a defect-free hexagonal array of concaves, which guide the pore growth during subsequent anodization. Among the numerous pre-patterning techniques, direct etching by focused gallium ion beam (Ga FIB) allows the preparation of AAO with a custom-made geometry through precise control of the irradiation positions, beam energy, and ion dosage. The main drawback of the FIB approach includes gallium contamination of the aluminium surface. Here, we propose a multi-step anodizing procedure to prevent gallium incorporation into the aluminium substrate. The suggested approach successfully covers a wide range of AAO interpore distances from 100 to 500 nm. In particular, anodization of FIB pre-patterned aluminium in 0.1 M phosphoric acid at 195 V to prepare AAO with the interpore distance of about 500 nm was demonstrated for the first time. The quantification of the degree of pore ordering reveals the fraction of pores in hexagonal coordination above 96% and the in-plane mosaicity below 3° over an area of about 1000 μm2. Large-scale defect-free AAO structures are promising for creating photonic crystals and hyperbolic metamaterials with distinct functional properties.

Optimization of Electrode Patterns for an ITO-Based Digital Microfluidic through the Finite Element Simulation.

Indium tin oxide (ITO)-based digital microfluidics (DMF) with unique optical and electrical properties are promising in the development of integrated, automatic and portable analytical systems. The fabrication technique using laser direct etching (LDE) on ITO glass has the advantages of being rapid, low cost and convenient. However, the fabrication resolution of LDE limits the minimum line width for patterns on ITO glasses, leading to a related wider lead wire for the actuating electrodes of DMF compared with photolithography. Therefore, the lead wire of electrodes could affect the droplet motion on the digital microfluidic chip due to the increased contact line with the droplet. Herein, we developed a finite element model of a DMF with improved efficiency to investigate the effect of the lead wire. An optimized electrode pattern was then designed based on a theoretical analysis and validated by a simulation, which significantly decreased the deformation of the droplets down to 0.012 mm. The performance of the optimized electrode was also verified in an experiment. The proposed simulation method could be further extended to other DMF systems or applications to provide an efficient approach for the design and optimization of DMF chips.

One-step in-situ low damage etching of SiC/SiC composites by high-temperature chemical-assisted laser processing

SiC/SiC composites have a promising application prospect in the fields of aero-engine turbine blades and other hot-end components due to their excellent properties. It is difficult to machine SiC/SiC composites by traditional mechanical processing because of the ultra-high hardness and anisotropic character. The routinely laser direct processing in the air produce thermal effect damage, resulting in heat-affected zones and microcracks. Here high-temperature chemical-assisted nanosecond laser processing was investigated to realize one-step in-situ fast etching without causing damage to the structure of SiC/SiC composites. Firstly, the chemical wet etching only occurred in the laser-induced local high-temperature region. There was no additional etching damage to the substrate material in the region where the temperature was relatively low. Secondly, chemical liquid served as a transparent constraint layer, the ablation pressure on the material increased in a liquid confined environment. In comparison with laser direct etching in the air, the exposed fiber was not a needle-like structure and tubular structure but turned into a thin and flat tongue-like structure. The etching behavior of 0° fiber layer, 90° fiber layer, and crossing regions of fibers of different directions at low and high laser intensities were studied. Further, the hardness and friction coefficient of SiC/SiC composites after laser direct etching in the air and high-temperature chemical-assisted laser etching were compared. The chemical elementary composition before and after etching was measured to reveal the oxidized and carbonized characteristics. It was concluded that the action mechanism was the combined result of high-temperature decomposition, laser-induced ablation pressure in the liquid confined region, and local chemical wet etching. The results demonstrate that high-temperature chemical-assisted laser etching has some advantages over traditional laser beam machining and is a potential processing method for SiC/SiC composites.

Fluoropolymer Passivation Enhanced Switching Endurance of MoS2 Memristors

The advances in computing and mobile devices have realized massive generation, collection, and processing of data. The concept "Internet of things" and "Big data" have necessiated large-scale parallel processing, as computing of collected data is highly dependent on matrix multiplication process, which in inherently parallel.In this context, conventional machines are exhibiting their limits as they are unsuited for parallel processing, resulting in low performance and high power consumption [1]. The need for advances in parallel processing hardware is emerging.In this regard, memristors have gathered attention for their high potentials as parallel processing units. There have been reports of memristors with high on/off ratio, fine retention, high switching enderance, and fast switching spped, etc [2-4]. Memristor is a non-volatile memory which stores data as internal resistance, modulated by applied voltage. Even though memristors contain high capabilities for parallel processing, scaling of devices still remain as a challenge. Conventional materials have their limit for both lateral and vertical scaling.To achieve a major breakthrough, we have fabricated memristors based on 2D materials with atomic-scale thickness of ~ 7 nm [5]. As surface-to-volume ratio is high in 2D materials, they are chemically active, leading to susceptible properties to external environment and instability in fabricated devices with 2D materials. To compensate the drawback, we applied fluoropolymer passivation layer and obtained stable switching endurance for 100 potentiation & depression cycles with 25 states.For device fabrication, we used direct current sputtering & wet etching to pattern bottom Au/Cr (50/5 nm) electrodes. Molybdenum disulfide flakes were mechanically exfoliated from bulk mineral and dry-transferred onto bottom electrodes by PDMS (Polydimethylsiloxane) stamps. Top electrodes were patterned by photolithography & evaporation of Ni/Au (5/100 nm).With the introduction of 2D materials to next-generation electronics, memristors can be even more revolutionized towards extreme scaling of devices. By compensating susceptibility in the material itself and studying degradation mechanism, parallel computing would be realized away from power-plugged environment, and accelerate artificial intelligence in our everyday lives. Figure Caption Fig 1. Electrical characterization of the resistive switching MoS2 memristor with non-volatile memory behavior. (a) Semi-log plots of IV curve, resistive switching triggered by voltage sweeping. Inset: False-color SEM image of a fabricated device; scale bar: 4μm. (b) Scheme for pulse voltages (top), potentiation and depression of conductance states (bottom). (c) Encapsulation-enhanced switching stability of MoS2 memristors. Detailed illustration of 20 PD cycles in CYTOP-encapsulated (top) and bare devices (bottom).

Development of Low Temperature Double Level TSV, Hole and Seal Process for Low Pressure Zero Level MEMS Packaging

Through Silicon Via (TSV) technology is considered one of the key methods to enable heterogeneous integration at the third dimension and realize electrical interconnection between device parts. In that context, different components (MEMS, sensors, circuits etc.) can be electrically integrated in 3D manner, increasing stack density, shrinking footprint, and reducing fabrication costs. At MEMS integration, it is important to explore the packaging method that enables the optimum performance of the active MEMS component and the TSV approach to electrically connect it with the package. Herein, we present our via-last approach to integrate a zero-level packaged MEMS wafer defined by cavity SOI (C-SOI) and CMOS readout circuitry (at thermal budget <400ºC). TSV distribution and fabrication route ensures the electrical connectivity of MEMS inertial sensor and CMOS. Furthermore, a hole is added to the layout scheme and sealed afterwards to ensure low pressure encapsulation in the MEMS cavity.In our previous work related to MEMS fabrication [1], we elaborated the superiority of C-SOI start material over conventional fabrication methods (like vapor HF). In our approach, MEMS cavity structures are realized by patterning dielectrics and the moving parts by employing deep Si etch (DSiE) method (Fig 1 a-c). To enhance the dielectric surface smoothness prior bonding, a complementary HF -based clean applied. This way, bonding requirements (Rq<1nm, Rrange<10nm) are met. CMOS wafer is fabricated with a single layer of Cu damascene process in a dielectric stack to create complementary bonding medium for MEMS wafer. Selected dielectrics at MEMS (thermal oxide) and CMOS (SiCN) can perform better at low temperature fusion bonding due to their moisture blocking capability. Next, fusion bonding at room temperature is carried out using assisted force (60kN) to enhance bonding efficiency and completed by curing the wafer pair at 350˚C.In this paper, we present further work to complete the MEMS zero-level packaging through electrical connections and vacuum seal. Fabrication sequence continues on the backside of the MEMS wafer (Fig 1d-g). First the desired top membrane (cap) thickness of MEMS wafer realized by thinning bulk Si substrate down to 50µm. After SiOx deposition, a double TSV approach is carried out aiming to create the electrical interconnections between the package components, one to reach to the sensor parts in MEMS wafer and one to reach to CMOS. TSV for enabling the connection with sensor parts (12x50μm) is realized by DSiE through the top Si membrane and buried oxide (BOX) landing at Si epi layer of C-SOI. Isolation of this TSV is obtained by conformal liner deposition using SACVD SiOx (350C). Liner opening at the TSV base is assisted by a second non-conformal dielectric deposition to protect the sidewall isolation during resistless directional liner etch back at TSV bottom. Metallization of the via is carried out by sequential PVD barrier (Ta) and seed (Cu) depositions; and the TSV is filled with electroplated Cu. MEMS top surface is then cleared either by CMP or by wet and dry etching of Cu and Ta, respectively. TSV for connecting to CMOS (20x80μm) follows the same processing route with an additional DSiE through all the C-SOI MEMS stack and landing on designated plugs on CMOS. With these two TSV schemes it is ensured to bias and measure the inertial sensor, its driving circuitry, and the zero-level package (Fig. 2a)Once the two TSVs fabrication is completed, hole for the vacuum sealing can be created. First, the top dielectric on surface of MEMS wafer is etched in circular areas of diameter 10μm to define where the venting holes will be created. This is mainly to expose Si surface and reduce possible leakage paths, as well as to increase the adhesion of the deposited metallization to close the hole under vacuum. Small hole (Ø2μm) is defined in the middle of the Si circular area by lithography and etching through the top MEMS membrane (50μm) landing on the cavity of the C-SOI (Fig 1f). Vacuum seal of the zero-level package is finalized with bond pad creation which also seals the hole under vacuum. Al deposition is carried out at high vacuum PVD system; the hole is simultaneously sealed and preserve the same vacuum as the PVD chamber. Along with the chamber vacuum level, the Al thickness and power is also very important to achieve the desired seal Fig.2b.Proposed work enables zero-level MEMS hermetic packaging with integrated CMOS and developed on 200mm wafers.[1] Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging, A.Malainou, J.Visker, D.Sabuncuoglu, 21st EPTC, Singapore 2019 Figure 1

Integrated Subwavelength Gratings on a Lithium Niobate on Insulator Platform for Mode and Polarization Manipulation (Laser Photonics Rev. 16(7)/2022)

Subwavelength Gratings In article number 2200130, Yonghui Tian and colleagues experimentally demonstrate compact subwavelength grating (SWG) waveguides on a LNOI platform for on-chip mode and polarization manipulation. To overcome the limitation of direct etching waveguide fabrication, a silicon nitride thin film was deposited onto the surface of LNOI chip, where the SWGs were formed using CMOS-compatible etching processes developed by microelectronics industry.

Length effect on the plastic deformation of SiO2 microcantilevers

SiO2 films are of much interest for the realization of suspended micromechanical structures such as microcantilevers and micro-bridges owing to their superior characteristics when compared to conventional c-Si. However, presence of residual stress induced bending and structural plastic deformation in these devices especially at elevated temperatures hinder their potential for real-time field applications. Moreover, the impact of micro-scale dimensional effects on the magnitude of deformation in these devices is not well understood. In this work, we have investigated the effect of post-release high temperature annealing on the bending and resonance frequency characteristics of SiO2 microcantilevers (MCs) with a specific focus on the length effect. For this purpose, SiO2 MCs of various lengths (Length: 50–190 μm, Width: 37 μm and thickness: 0.98 μm) were fabricated using direct laser writer and wet chemical etching methods and were subjected to high temperature annealing under N2 and O2 environments. We demonstrate through our experiments that the curvature of SiO2 MCs increases with both annealing temperature and length square of MCs. Our experiments revealed that, apart from onset of plastic deformation, stress accumulation at the fixed end of SiO2 MCs is also responsible for the observed curvature increase. From the measured curvature, mean (σ0) and gradient (σ1) residual stress values were estimated and found to increase with annealing temperature. Interestingly, there exists a critical length of MCs (90 μm) below which both σ0 and σ1 were found to increase further with reducing MC length and is shown to be due to the existence of large transverse curvature at these dimensions. High temperature annealing was also found to increase the resonance frequency of MCs and the increase was maximum ∼ 8% for 130 μm long MC. Various possible reasons for the frequency shift is discussed in detail.

Facile Morphology and Porosity Regulation of Zeolite ZSM-5 Mesocrystals with Synergistically Enhanced Catalytic Activity and Shape Selectivity

The morphology and mesoporosity of zeolite are two vital properties to determine its performance in diverse applications involving adsorption and catalysis; while it remains a big challenge for the synthesis and regulation of zeolites with exceptional morphology/porosity only through inorganic-ions-based modification. Herein, by simply optimizing the alkali metal type (K+ or Na+), as well as alkali/water ratio and crystallization temperature, the zeolite ZSM-5 mesocrystals with diverse mesostructures are simply and controllably prepared via fine-tuning the crystallization mechanism in an organotemplate-free, ions-mediated seed-assisted system. Moreover, the impacts of these key parameters on the evolution of seed crystals, the development and assembly behavior of aluminosilicate species and the solution-phase process during zeolite crystallization are investigated by means of directional etching in NH4F or NaOH solutions. Except for the morphology/mesoporosity modulation, their physical and chemical properties, such as particle size, microporosity, Si/Al ratio and acidity, can be well maintained at a similar level. As such, the p/o-xylene adsorption and catalytic performance of o-xylene isomerization are used to exhaustively evaluate the synergistically enhanced catalytic activity and shape selectivity of the obtained products. This work demonstrates the possibility of effectively constructing novel zeolite mesostructures by simply altering parameters on simple ions-controlled crystallization and provides good models to inspect the impacts of mesoporosity or morphology on their catalytic performances.

Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below

Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of &amp;lt;10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implemented without barrier. An integration scheme with direct metal etch instead of damascene patterning could simplify the overall patterning flow and eventually opens the possibility for exploring new integration concepts and patterning approaches. However, the learning on direct metal etch of Ru and Mo in the literature is scarce, especially at the relevant dimensions of today's interconnects. In this work, we will focus on the major patterning challenges we have encountered during the development of direct metal etch processes for Ru at 18 nm pitch and Mo gratings at 32 nm pitch. We have observed that the direct metal etch of Ru at these small dimensions is impacted by the growth of an oxidized layer on the sidewalls of the hard mask, which originates from the sputtering of the hard mask in combination with the O2-based Ru etch chemistry. This results in a narrowing of the trenches to be patterned and can easily lead to an etch stop in the smallest features. We will discuss several mitigation mechanisms to remove this oxidized layer, as well as to avoid the formation of such a layer. For patterning Mo with a Cl2/O2-based chemistry, the major patterning challenges we encountered are the insufficient sidewall passivation and the oxidation of the patterned Mo lines. The sidewall passivation issue has been overcome with an in situ thin SiO2-like deposition after partial Mo etch, while a possible mitigation mechanism for the Mo oxidation could be the in situ encapsulation immediately after Mo patterning.

Improved PDMS mold fabrication by direct etch with nanosphere self-assembly mask for Soft UV-NIL subwavelength metasurfaces fabrication

With the increased relevance of metasurface for optical applications, a fabrication method that allows for both large surface and 100 nm range dimensions at a low cost is required for their development. Due to its high throughput and small structuration capabilities, Soft Nanoimprint Lithography is a good canditate as fabrication method for these type of devices. But its application for metasurfaces at visible wavelengths has been hindered by the necessity to use low-viscosity PDMS in order to reach the dimensions required, making the final stamp more fragile and the process more expensive. Here we propose a PDMS mold fabrication method which relies on self-assembly masking of the PDMS followed by direct etching of the mold, decorrelating the minimum dimension attainable from the PDMS viscosity. We characterize a metasurface fabricated using a mold obtained with our method validating its use for nanofabrication of large surface devices.

Directional etching for high aspect ratio nano-trenches on hexagonal boron nitride by catalytic metal particles

Stimulated by the attractive performance of multi-dimensional heterostructures involving hexagonal boron nitride (hBN), intense attentions have been paid to creation of sharp boundary/interface, which could bring hBN nano-structures additional appealing physical properties. However, the lack of controllable synthesis limits further experimental investigation on hBN nano-structures. Here, the directional etching of transitional metal nano-particles (NPs) on the surface of hBN to produce nano-trenches with sharp edges was systematic investigated. It is found that, only Pt and Ir NPs can produce armchair-oriented nano-trenches at low H2 partial pressure, while other transitional metals lead to zigzag oriented nano-trenches. The density and width of the nano-trenches always increase with etching temperature and the pre-treated solution concentration while the trench orientation depends on both H2 partial pressure and etching temperature. The aspect ratio of nano-trenches may reach several thousand under optimized conditions. The method exhibited here shines a light on edge-selective patterning of 2D crystals.

Constructing TiO2@CeMnOx nanocages by self-sacrificial hydrolytic etching MIL-125 for efficient wide-temperature selective catalytic reduction of nitrogen oxides

A nanocage-confined composite catalyst TiO2@CeMnOx-NC was carefully designed and fabricated by directional hydrolytic etching of MIL-125. With the directional protection of tannic acid and PVP used as stabilizer agents, MIL-125(Ti) was controllably etched from its inside out by self-hydrolysis. Notably, MnOx was encapsulated into the cavity of the TiO2 nanocage, and CeO2 was mainly anchored on its outside surface. With the help of related characterization methods, it was found that amorphous TiO2 formed after annealing, and fluorite cubic structured CeO2 inhibited the crystallization of MnOx clusters. Thanks to this unique structure, strong metal-support interactions occurred between Ce/Mn oxides and TiO2, which dramatically enhanced its surface acidity and adsorption ability. Besides, the redox capacity has also been significantly affected. Consequently, the carefully designed composite confined TiO2@CeMnOx-NC with a nanocage structure showed excellent NH3-SCR catalytic performance over a wide working temperature window. In addition, benefiting from the double protection of TiO2 nanocages and CeO2 on the outer surface, the MnOx encapsulated in the cavity could be effectively protected from the influence of water vapor in the flue gas, thus exhibiting good water resistance. In situ DRIFTs analysis revealed that the NH3-SCR process on TiO2@CeMnOx-NC mainly followed the Eley-Rideal (E-R) reaction mechanism. Comparing with nanosheets TiO2@CeMnOx-NS and nanoparticles TiO2@CeMnOx-NP, the nanocages TiO2@CeMnOx-NC have more promising prospects in NH3-SCR applications.