Direct Sampling Receiver Research Articles

A reconfigurable RF front-end for 5G direct sampling receivers with an optimized calibration scheme

This paper presents a reconfigurable radio frequency front-end (RFFE) tailored for direct RF sampling receivers operating within Frequency Range 1 (FR-1) of the 5G spectrum. It consists of a balun-LNA, a noise-cancelling, current-reuse, Q-enhanced filter, and a programmable gain amplifier (PGA). Fabricated in 22-nm FD-SOI technology, the RFFE covers the entire frequency range from 1.7 to 6.4 GHz with a tunable bandwidth ranging from 50 MHz to 1.2 GHz. The experimental results confirm that the RFFE achieves 3.9 dB NF, 55 dB ultimate OOB rejection, −4 dBm IB-IIP3, and 23 dBm OOB-IIP3. Furthermore, a digital calibration scheme is proposed to compensate for process, voltage, and temperature (PVT) variations, achieving lower than 2 % error in 6.61 µs on average. Subsequently, a proximal policy optimization (PPO) agent is employed to choose the optimal policy for the successive adjustments of quality factors and resonance frequencies of the filter’s resonators. As a result, the proposed reinforcement learning algorithm reduces the calibration’s convergence time by 59 %.

A Re-configurable Body Channel Transceiver towards Wearable and Flexible Biomedical Sensor Networks.

Body channel communication (BCC) has become a promising candidate in wireless body area networks (WBAN) due to its advantages in energy efficiency and security. However, BCC transceivers face two challenges: diverse application requirements and varying channel conditions. To overcome these challenges, this paper proposes a re-configurable architecture for BCC transceivers (TRXs), whose key parameters and communication protocols can be software-defined (SD) according to the requirements. In the proposed TRX, the programmable direct-sampling receiver (RX) is a combination of a programmable low-noise amplifier (LNA) and a fast-convergent successive approaching register analog-to-digital converter (SAR ADC), to achieve simple but energy-efficient data reception. The programmable digital transmitter (TX) is essentially implemented by a 2-bit DAC array to transmit either wide-band carrier-free signals like 4-level pulse amplitude modulation (PAM-4) or non-return-to-zero (NRZ) or narrow-band carrier-based signals like on-off keying (OOK) or frequency shift keying (FSK). The proposed BCC TRX is fabricated in a 180-nm CMOS process. Through an in-vivo experiment, it achieves up to 10-Mbps data rate and 119.2 pJ/bit energy efficiency. Moreover, the TRX is able to communicate under long-distance (1.5 m) and body-shielding conditions by switching its protocols, which shows the potential to be deployed in all categories of WBAN applications.

A Fully Integrated 0–200-MHz System BW Wireless Direct Sampling Receiver in 14-nm FinFET

This paper presents a fully-integrated wireless direct sampling receiver that covers from DC to 200MHz system bandwidth implemented with a single-channel SAR ADC in 14nm FinFET. To demonstrate the proposed architecture, frequency modulation (FM) among the applicable standard frequency bands is adopted as a prototype. The measured demodulated SNR is 73.9dB with -47dBm input power at 108MHz and the sensitivity level is -106dBm. The proposed direct sampling receiver shows a robust performance over a 30dB demodulated SNR even in the presence of the interference such as a strong adjacent channel and an in-band spur. Furthermore, the FM channel scan time is drastically reduced since the proposed receiver simultaneously samples all channels without adjusting analog building blocks.

Concurrent Multiband Direct RF Sampling Receivers

Direct radio frequency (RF) sampling receivers are investigated for use in concurrent multiband reception for mobile broadband (MBB) applications. The recent proliferation of different frequency bands and standards in wireless communications has allowed large increases in mobility and throughput, but the number of receivers in a device is limited by physical space and power consumption. Software Defined Radio (SDR) is increasingly being explored to reduce the number of analog RF components required. This paper examines the use of direct RF digitization, allowing tunable and concurrent reception of multiple bands with a single RF front-end. Full mathematical models of both Nyquist and subband sampling receivers are presented and used to investigate a quadband LTE receiver, which is modeled in Simulink and implemented in a hardware-in-the-loop (HWIL) testbed. Individual bands are simulated to have at worst -95dBm sensitivity for 16-QAM with Nyquist sampling and -83dBm with subband sampling. Desensitization of the receivers due to multiband processing is evaluated theoretically and experimentally, showing a maximum of 3dB degradation, which is within the LTE standard for adjacent band interference.

Theoretical Analysis and Design Optimization for Multi-GNSS Direct Radio Frequency Sampling Receiver

Abstract: Recently, a considerable amount of research has been conducted on multiple GNSS receivers using the Direct RF sampling concept. This approach greatly reduces the hardware requirements of the traditional receiver by placing the analog-todigital converter as close as possible to the antenna, eliminating the mixer stages. Furthermore, directly sampling the RF signal using the ADC allows for a more efficient design. In this paper, a Multi-GNSS Direct Radio Frequency Sampling Method is designed, optimized, and its performance is presented for several GNSS signals, including GPS L1, GPS L2, and GPS L5. The implemented method is used to find the ranges of valid sampling frequencies in single and multiple band RF signal cases. The algorithm presented results in an easier way to find valid sampling frequencies and a straightforward implementation without the need for complicated mathematical calculations. We consider aliasing issues and computational problems, providing a full theoretical and practical analysis compared to previously presented algorithms in the literature. This paper also examines the relationship between the sampling frequency, noise folding, and its effect on the signal-to-noise ratio (SNR), thus allowing for the selection of the optimal sampling frequency.

A system‐level performance evaluation of a reconfigurable filtenna in the presence of in‐ and out‐of‐band blockers

Direct RF sampling has been suggested as a solution for receivers that are flexible in frequency and across standards, while utilising only a single radio frequency front-end. However there are concerns about their robustness in the presence of out-of-band and in-band blockers. Tunable filtennas offer a solution to this, incorporating filtering into the antenna space while providing rejection of unwanted signals. This paper presents a filtenna containing reconfigurable frequency selective surfaces to provide tunable filtering between 1.44 and 1.95 GHz. The filtenna is characterised as an antenna and a filter, showing minimum 18 dB rejection across the principle beamwidths. It is then implemented in a direct RF sampling receiver and is shown to provide sufficient rejection of blockers to cause no degradation in the received error vector magnitude (EVM) and block error rate (BLER) of LTE signals when subject to 5G NR-compliant blocking signals. The in-band blocker performance is also characterised, showing at most 3 dB degradation in EVM and BLER.

Development of a direct-sampling RF receiver for precision beam charge measurements in the MOLLER experiment

We have developed and tested a direct-sampling RF receiver capable of measuring the amplitude of a 1497 MHz sinusoidal beam signal in 0.5 ms integration windows with a relative uncertainty of better than 10 parts per million. The receiver is intended for measuring signals from beam current monitoring cavities on the beamline of the Continuous Electron Beam Accelerator Facility (CEBAF) at Jefferson Lab. The beam signal strength, frequency, and integration window fulfill the thus far unmet requirements of the upcoming MOLLER experiment to measure the beam charge for different helicity states.

A LUT-based scheme for LNA linearization in direct RF sampling receivers

Direct RF sampling receiver – a fully digital receiver architecture – undoubtedly becomes a favored choice for HF/VHF as this approach inherently bypasses the legacy nonlinearities caused by analog components. In DRF-RF and wideband multichannel in general, LNA is still an indispensable component to ensure the receiver’s sensitivity. However, with the presence of multiple channels, the total RF power often surpasses the linear threshold that LNA and the amplified signal become severely distorted. This paper proposed a method for mitigating the LNA distortion using the look-up table (LUT) approach. Specifically, our receiver is designed with two modes of operation. In training mode, a built-in signal circuit generates a training signal for extracting the LNA characteristic and eventually reconstructs the inverse LNA nonlinear model in the form of a LUT memory. During the receiving mode, a linearization circuit reverses the distortion impact by matching the RF power level with the inverse nonlinear model pre-stored in the LUT. The effectiveness of the proposed distortion compensation method first is evaluated by a MATLAB simulation with a multi-channel DRF-RF model. The simulation results show that the proposed approach significantly improved the SNDR for the channel of interest. Furthermore, the model has been practically verified, where the actual distorted signals are sampled from a commercial LNA (ZFL-500LN+) by a customized FPGA board. Results from measurements show an improvement of ∼7 dB for SNDR and 27% for EVM in a strong distortion scenario of QPSK modulation signal.

Fully digital background calibration of channel mismatches in time-interleaved ADCs using recursive least square algorithm

Time-interleaved analog-to-digital converters (TIADCs) have been considered as a very promising solution for high-speed direct sampling receivers. However, channel mismatches reduce the TIADC’s performance significantly. Therefore, calibration of these mismatches is emerging to maintain the performance of these TIADCs. This paper proposes a fully digital background calibration technique for multiple deviations including offset, gain, and timing mismatches. Offset and gain deviations in TIADCs are sequentially calibrated by taking the average value of the output samples, and calculating the ratios of power, respectively. Then, the timing mismatch is compensated by using the Hadamard matrix and the adaptive recursive least square (RLS) algorithm. The proposed calibration technique is proven through the simulation results for signal-to-noise-and-distortion (SNDR), spurious-free dynamic range (SFDR) and time convergence. As a result, the performance of TIADC is improved by 40.98 dB and 70.64 dB for SNDR and SFDR, respectively.

A Comprehensive Study of Adaptive LNA Nonlinearity Compensation Methods in Direct RF Sampling Receivers

This paper studies the effects of nonlinear distortion of Low Noise Amplifier (LNA) for the multichannel direct-RF sampling receiver (DRF). The main focus of our work is to study and compare the effectiveness of the different adaptive compensation algorithms, including the inverse-based and subtract-based Least Mean Square (LMS) algorithm with a fixed and variable step size. The models for the compensation circuits have been analytically derived. As the major improvements, the effectiveness of the compensation circuits under the ADC quantization noise effect is evaluated. The bit-error-rates (BER) in dynamic signal-to-noise ratio (SNR) scenarios are calculated. We have proposed the use of variable step-size LMS (VLMS) to shorten the convergence time and to improve the compensation effect in general.
 To evaluate and compare different compensation methods, a complex Matlab model of the Ultra high frequency (UHF) DRF with 4-QPSK channels was implemented. The simulation results show that all compensation methods significantly improve the receiver performance, with the convergence time of the VLMS algorithm does not exceed 5.104 samples, the adjacent channel power ratios (ACPR) are reduced more than 30 dBc, and the BERs decrease by 2­–3 orders of magnitude, compared with the non-compensated results. The simulation results also indicate that the subtraction method in general has better performance than the inversion method.

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications

This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to obtain the derivative of the autocorrelation of the input signal, subsequently used to evaluate the explicit amount of the timing-skew. Therefore, this allows a digital background calibration of the timing-skew, avoiding extra analog circuits. The proposed 16-channel TI ADC uses a splitting-combined monotonic DAC switching method for the individual SAR channel to achieve a trade-off of simple switching and small common-mode voltage variation of the comparator. The prototype, implemented in 28 nm CMOS, reaches a 48.5/47.8 dB SNDR with an input signal of 2.38/4.0 GHz after the proposed background timing mismatch calibration, respectively. Furthermore, the ADC core’s power consumption is 29 mW sampling at 5 GS/s, with a Walden FoM of 26.7 fJ/conv.-step and a Schreier FoM of 157.9 dB.

A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers

This paper presents a comparative analysis between two new architectures for RF programmable-gain amplifiers (RFPGAs): voltage-mode RFPGA-V and current-mode RFPGA-I. RFPGA-V utilizes multiple-switch-multiple-amplifier configuration and gain interpolation method to achieve a fine gain step of 0.25-dB over 42-dB gain range for the band of 250 MHz to 2.3 GHz. Meanwhile, RFPGA-I uses a current steering approach to achieve a fine gain step of 0.25-dB over 42-dB gain range for an even wider band of 250 MHz to 3.4 GHz. Since the active feedback topology is used, no off-chip inductor is needed in either RFPGA, especially for the low-frequency band. In addition, both RFPGA-V and RFPGA-I are able to handle maximum 4.4 V peak-to-peak input signal without compromising their high operating bandwidth. Two broadband RF front ends for direct sampling receivers, which include either RFPGA-V or RFPGA-I followed by the same gain buffer and RF filter, have been demonstrated. For the RF front end with RFPGA-V, the measured gain, noise figure, third-order input-referred intercept point (IIP3), and second-order input-referred intercept point (IIP2) in the differential mode are 29.5 dB, 5.2 dB, −10.9 dBm, and 31.4 dBm, respectively. With RFPGA-I, they are 30.5 dB, 3 dB, −10.5 dBm, and 21.1 dBm, respectively. Both RF front ends consume approximated 50 mW and occupy the similar area of 0.32 mm2 in 28-nm CMOS technology.

A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential.

다중대역 GNSS 신호 동시 수신을 위한 직접 RF 표본화 수신기 설계 및 성능

이 논문에서는 GNSS(global navigation satellite system) 신호를 RF(radio frequency) 대역에서 표본화하여 디지털 영역에서 복조하는 직접 RF 표본화 수신기를 설계하고 그 성능을 살펴보고자 한다. 직접 RF 표본화 방식은 IF(intermediate frequency) 대역에서 AD(analog to digital) 변환을 하고 복조하는 기존의 IF 변환 방식과 다르게, 아날로그 믹서(mixer)를 전혀 사용하지 않고 안테나 출력인 통과대역 신호를 직접 AD 변환하여 이후의 수신기의 모든 과정을 디지털 영역에서 처리하는 기술이다. IF 변환 방식과 비교하면 하드웨어 구조가 덜 복잡하고 전송환경 변화에 따른 재구성이 가능하며 하나의 AD 변환기를 사용하여 여러 대역의 신호를 동시에 변환할 수 있다는 장점이 있다. 이와 같은 재구성 기능과 동시 수신 기능은 특정 대역의 신호가 적으로부터 전파방해를 받았을 때 후속시스템으로의 빠른 전환이 필요한 군용 시스템에서 매우 중요한 역할을 한다. 한편 여러 대역의 신호를 한 번에 AD 변환하려면 수신하고자 하는 신호의 반송파 주파수, 대역폭, 표본화 후의 중간주파수 그리고 보호 대역 등을 고려하여 표본화 주파수를 정하는 것이 중요하다. 이 논문에서는 GPS L1, GLONASS G1 및 G2 등의 GNSS 신호를 동시에 수신할 수 있는 표본화 주파수를 선택하고 이를 적용한 직접 RF 표본화 수신기를 설계한다. 또한 설계한 수신기를 상용 AD 변환기와 소프트웨어를 사용하여 구현한 후 실제 신호의 수신시험을 통해 수신 성능을 살펴본다. In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

Theoretical Comparison of Direct-Sampling Versus Heterodyne RF Receivers

An intuitive high-level argument is presented suggesting that direct-sampling radio frequency (RF) receivers using Nyquist analog–digital converters can be as power-efficient as analog heterodyne receivers for equal dynamic range specifications, at least at lower RF frequencies well below the $f_{t}$ of the IC process. System planning for direct-sampling receivers is reviewed, highlighting dBFS/Hz as an intrinsic measure of dynamic range, independent of channel and Nyquist bandwidths. Power dissipation versus dynamic range for recently reported heterodyne and direct-sampling receivers is examined.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies $1 \text{ mm}^{2}$ area while consuming 300 mW. The LNA consumes 130 mW and occupies $3 \text{ mm}^{2}$ area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves ${-}$ 61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves ${-}$ 54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is ${ 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm $^{2}$ .

Structure of Direct RF Sampling Receivers for GNSS Signals

A direct RF sampling method refers to a technique that directly converts a passband signal to an intermediate band or a baseband without using a mixer. This method is less complicated than an existing RF receiver because a mixer is not used. It uses digital processing after sampling, and thus can flexibly process signals in a number of bands using software. In this process, it is important to select an appropriate sampling frequency so that a number of signals can be converted to an intermediate band that is easy to process. In this study, going beyond previously studied direct RF sampling frequency selection methods, conditions that need to be additionally considered during receiver design were examined, and the structure of a direct RF sampling receiver that satisfies these conditions was suggested.

A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS

This paper presents a ultra-wideband (UWB) impulse radio timed-array radar utilizing time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the receiver determines the time of arrival (TOA), and a four-element timed antenna array enables beamforming. The different time shifts among the channels at the receiver determine the object's direction of arrival (DOA). Transmitter channels have different shifts, as well, to enhance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip digital-to-time converter (DTC) provides all the necessary timing with a fine resolution and wide range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18- μm standard CMOS technology with a die size of 5.4×3.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 5.4×5.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the transmitter and the receiver, respectively.

High‐resolution reduced field of view diffusion tensor imaging using spatially selective RF pulses

Diffusion tensor imaging (DTI) plays a vital role in identifying white matter fiber bundles. Achievable imaging resolution and imaging time demands remain the major challenges in detecting small fiber bundles with current clinical DTI sequences. A novel reduced field of view ultra-high-resolution DTI technique named eZOOM (elliptically refocused zonally oblique multislice) was developed. A small circular disk was imaged using spatially selective radiofrequency (RF) pulses, reducing the imaging matrix size. The frequency profile of the spectral-spatial refocusing RF pulse provided intrinsic fat suppression, eliminating the need for fat saturation pulses. Multislice DTI at a resolution of 0.35 × 0.35 mm in a celery fiber phantom was successfully performed by scanning an 8-cm field of view at 3T. An adequate diffusion-to-noise ratio (DNR >20) was achieved for a 25-min acquisition using a direct-sampling RF receiver. Human subjects (n = 7) were scanned at resolutions of 0.47 × 0.47 mm having a DNR <20 within a 75-min scanning time, requiring further enhancements to increase the signal-to-noise ratio. The new eZOOM-DTI method offers multislice DTI at ultra-high imaging resolutions substantially exceeding those available with current echo-planar DTI techniques. Parallel and fast spin echo methods can be combined with eZOOM to improve SNR and DNR in humans.