A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers

Abstract

This paper presents a comparative analysis between two new architectures for RF programmable-gain amplifiers (RFPGAs): voltage-mode RFPGA-V and current-mode RFPGA-I. RFPGA-V utilizes multiple-switch-multiple-amplifier configuration and gain interpolation method to achieve a fine gain step of 0.25-dB over 42-dB gain range for the band of 250 MHz to 2.3 GHz. Meanwhile, RFPGA-I uses a current steering approach to achieve a fine gain step of 0.25-dB over 42-dB gain range for an even wider band of 250 MHz to 3.4 GHz. Since the active feedback topology is used, no off-chip inductor is needed in either RFPGA, especially for the low-frequency band. In addition, both RFPGA-V and RFPGA-I are able to handle maximum 4.4 V peak-to-peak input signal without compromising their high operating bandwidth. Two broadband RF front ends for direct sampling receivers, which include either RFPGA-V or RFPGA-I followed by the same gain buffer and RF filter, have been demonstrated. For the RF front end with RFPGA-V, the measured gain, noise figure, third-order input-referred intercept point (IIP3), and second-order input-referred intercept point (IIP2) in the differential mode are 29.5 dB, 5.2 dB, −10.9 dBm, and 31.4 dBm, respectively. With RFPGA-I, they are 30.5 dB, 3 dB, −10.5 dBm, and 21.1 dBm, respectively. Both RF front ends consume approximated 50 mW and occupy the similar area of 0.32 mm2 in 28-nm CMOS technology.