Direct-current Current-voltage Research Articles

Measurement-Based Nonlinear SPICE-Compatible Photovoltaic Models for Simulating the Effects of Surges and Electromagnetic Interference within Installations

An emerging area of interest within photovoltaic (PV) centred research is the simulation of the propagation of electromagnetic interference (EMI) and surges within PV installations. An overarching constraint in all simulation-based research is the accuracy of the models employed. In general, for PV-focussed simulations, nonlinear models are utilised for direct current (DC) analyses, whilst linearised models are employed for analyses involving surges or conducted electromagnetic interference. For large-signal electromagnetic interference and surges, the following two problems arise: (1) the aforementioned linearisation is only valid for the small-signal case, and (2) as they are constructed using only DC measurements, traditional large-signal PV models are generally only valid for DC conditions. Therefore, neither of these approaches can properly represent real-world PV behaviour under dynamic conditions. To overcome this limitation, this article proposes a more suitable model, compatible with Simulation Program with Integrated Circuit Emphasis (SPICE), and which results from the combination of two sub-models: one for large-signal DC cases, and one for small-signal alternating current (AC) cases. Consequently, the combined model enables improved modelling of the effects of large-signal transient perturbations to be performed, as well as cases involving small-signal AC and large-signal DC perturbations. The model parameters are extracted using data from two different classes of measurement setups: the first utilised a vector network analyser (VNA) to produce small-signal AC impedance results (covering a frequency range between 1 Hz and 50 MHz), and the second produces DC current-voltage curves. Both classes of measurement setup consider the device under test at multiple operating points. Key results include: (1) an improved SPICE-compatible PV model which caters for large-signal transient simulations, as well as for small-signal AC and large-signal DC cases, (2) improvements in the modelling of reverse bias behaviour when compared to the standard SPICE diode implementation, (3) the correct implementation of a voltage-dependent total capacitance (suitable for large-signal simulations), (4) modelling parameters for both a small (10 W) and a large (310 W) PV module, (5) measurement results which de-embedded the parasitic effects of the test setups employed, and (6) above 1 MHz, the physical layouts of the cells within the PV modules begin to influence the observed impedances.

(Digital Presentation) Optimization of MIM Rectifiers for Terahertz Rectennas

There is a significant demand for harvesting renewable infrared (IR) energy from unused heat sources. The rectifying antenna (rectenna) device has the ability to capture alternating current (AC) IR radiation and rectify it into usable direct current (DC) electricity. Metal-Insulator-Metal (MIM) diodes have shown to be the most prominent contenders for rectenna applications. This is due to their ultra-fast current transport mechanism in the femtosecond range by means of quantum mechanical tunnelling. Optical rectification at 28.3 THz has recently been demonstrated by rectenna devices based on MInM diodes using Au/Al2O3/Ti [1] and Ti/TiO2/ZnO/Al [2] configurations. Although the results are promising, the overall conversion efficiency is quite low, 2.05 × 10-14 [1], mainly due to the poor rectification properties of the diodes. Other recent research [3-5] has focused on the combination of stoichiometric and non-stoichiometric oxides with the aim of engineering the barrier heights to achieve low dynamic resistance (R0 ), high responsivity (β0 ) and asymmetry (η0 ) at zero-bias where the results are very promising for self-biased rectennas. The most recent experimental breakthrough was achieved by Ni/NiO/AlOx/CrAu bowtie rectennas that feature a device area of 0.035 µm2, low R0 of 13 kΩ and high β0 of 0.5 A/W. The results show that 5.1% coupling efficiency and 1.7 × 10−8% power conversion efficiency can be achieved with correct optimization of oxide stack. Furthermore, the most recent theoretical study [6] shows that the β0 of the MI2M diodes can be further improved to ~ 5 A/W by keeping the impedance match between the diode and the antenna at around 100 Ω. The proposed Ti/1 nm TiO2/1 nm Nb2O5/Ti rectenna design can achieve diode cut-off frequency (fc ) of 17 THz and resistance × capacitance (RC) time constant of 9 fs assuming the diode area of 0.01 µm2. Liverpool group has demonstrated recently [7,8] the effect of resonant tunnelling in non-cascaded (Al/Ta2O5/Nb2O5/Al2O3/Al) and cascaded (Al/Nb2O5/Al2O3/Ta2O5/Al) triple insulator diode structures with an oxide thickness ratio of 1:3:1 (in nm) deposited by atomic layer deposition (ALD). The diodes exhibit superior β = 5 A/W at 0.2 V and η = 12 at 0.1 V, with a drawback of high R0 due to high barrier heights between the metal/oxide layers.In this paper, we further optimize the MInM diode configurations so that the metal/oxide barrier is significantly lowered to ~ 0.1 eV. This is achieved by using the combinations of rectenna contender oxides such as Al2O3, NiO and ZnO that have high electron affinity and low dynamic permittivity [9]. Ultra-thin (≤ 5 nm) insulating layers were fabricated using radio frequency (RF) magnetron sputtering and ALD. Metal electrodes were deposited by thermal evaporation and RF sputtering using shadow mask, photolithography and nanolithography processes. The device areas range from 100 µm × 100 µm, 1 µm × 1 µm and 100 nm × 100 nm depending on the patterning process to observe the effect of device scaling on the conduction mechanisms and direct current (DC) rectification properties. The deposited oxide layers were measured by variable angle spectroscopic ellipsometry (VASE) to ascertain their thickness, uniformity and optical constants. DC current voltage measurements were performed on fabricated diodes to evaluate key rectification parameters such as R0 , β0 , η and non-linearity (fNL ) around zero-bias. Complementary theoretical calculations were performed to substantiate the experimental results and allow comparison of different MInM diode configurations such as NiO/Al2O3, ZnO/Al2O3, NiO/ZnO and NiO/ZnO/Al2O3. This work shows that the coupling efficiency at IR cut-off frequencies can be improved by optimizing the barriers in MInM rectifiers. References. [1] Jayaswal et al.,Materials Today Energy, 7, 1-9 (2018); [2] Elsharabasy et al., IEEE J. Photovoltaics, 9, 1232, (2019); [3] Matsuura et al., Sci. Rep. 9, 1-7 (2019); [4] Weerakkody et al., ACS Appl. Nano Mater. 4, 2470–2475 (2021); [5] Belkadi et al., Nat. Commun., 12, 1–6 (2021); [6] Elsharabasy et al., Results Mater. 11, 100204 (2021); [7] Mitrovic et al., ECS Trans. 72, 287 (2016); [8] Tekin et al., Solid State Electron. 185, 108096 (2021); [9] Mitrovic et al., Materials, 14, 5218 (2021).

The Measurement and SPICE Modelling of Schottky Barrier Diodes Appropriate for Use as Bypass Diodes within Photovoltaic Modules

The modelling of surges within PV (photovoltaic) installations has been the subject of much research in recent years. However, accurate simulations cannot be performed unless each and every component within a PV installation is modelled in sufficient detail. The bypass diodes within a PV module are frequently omitted from such simulations. When included, they are often represented by oversimplified models. This article addresses this need by presenting SPICE (Simulation Program with Integrated Circuit Emphasis) models for three Schottky diodes, chosen due to their suitability for use as bypass diodes. These models are the combination of DC (direct current) large-signal and AC (alternating current) small-signal sub-models, which are integrated such that the resulting full circuital models allow for accurate simulations involving large-signal transient stimuli. Two types of experimental setups, one incorporating a DC current–voltage curve sweep, and the other involving VNA-based (vector network analyser) AC small-signal impedance measurements, allow for the acquisition of the necessary model parameters at multiple operating points. The AC small-signal measurements cover a wide bandwidth of 100 Hz to 50 MHz. Multiple configurations of the measurement setups are employed in order to achieve the required dynamic range and sensitivity.

Evidence of Hot-Hole Induced Degradation in Lateral NDRIFT MOSFET: Characterization and TCAD Analysis

The role of secondary hot holes in the degradation of n-channel lateral drift MOSFETs, possibly leading to gate oxide breakdown, is discussed. Trapping of positive charges in the gate and field oxides and the formation of interface states under hot-carrier stress (HCS) have been successfully monitored by means of direct current current-voltage (DCIV) measurements and through gate-drain capacitance measurements. Experimental data have been complemented with Technology Computer Aided Design (TCAD) analysis. A degradation model including both hot-electrons and secondary hot-holes induced degradation capable of interpreting and reproducing measured data is proposed. Simulations allow to gain insights in the kinetics laws governing charge trapping and interface states generation along the silicon/oxide interface. The drift kinetics of the ON-state resistance have been also characterized and reproduced by simulations.

Torus breakdown in a two-stroke relaxation memristor

Experimental study of a two-stroke relaxation oscillator (TSO) has enabled to show that this electronic component has the same features as the so-called “memristor”. So, we have used the memristor’s direct current (DC) vM−iM characteristic for modeling the TSO’s DC current-voltage characteristic. This led us to confirm on one hand, that the TSO is a memristor and, on the other hand to propose a new four-dimensional autonomous dynamical system allowing to describe experimentally observed phenomena such as the transition from a limit cycle to torus breakdown.

Recovery Behavior of Interface Traps After Negative Bias Temperature Instability Stress in p-FinFETs Featuring Fast Trap Characterization Technique

We present an experimental study on the recovery feature of generated interface traps (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) after the application of dc/ac negative-bias temperature instability (NBTI) stress in Si p-FinFETs using a fast direct-current current-voltage method. In addition to the delayed recovery that typically occurs after a 10-ms recovery time, the immediate recovery of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> IT</sub> starting within a recovery time of 400 μs is observed, which is missing in the current reaction-diffusion model. In this study, this immediate recovery is systematically investigated under different stress modes and is attributed to the accumulation of H atoms. Furthermore, when the accumulated H atoms in a pulse-on phase are quickly consumed in the following pulse-off phase, a widely reported delayed recovery after Mode-B ac stress is observed.

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devices. It is illustrated that the high P-type impurity concentration near back interface makes it more difficult to break up silicon hydrogen bonds, which gives the PX devices superiority in resisting the build-up of interface traps. The study results indicate that increasing doping concentration of the body region near the back-gate interface might be an alternative radiation hardening technique of SOI MOSFET devices to avoid the parasitic back transistors’ leakage.

Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

Effect of Radiation on Interface Traps of SOI NMOSFETs by the Direct-Current Current-Voltage Technique

This paper investigates the effect of total ionizing dose radiation on back-gate interface traps in SOI NMOSFETs. The concentration and energy distribution of interface traps at Si/SiO 2 back-gate interface of SOI NMOSFETs during irradiation are studied by the direct-current current-voltage technique. When transistors are subjected to radiation, DCIV bulk current increases. The calculated results suggest that the interface trap density increases and its equivalent energy level is far away from the midgap with irradiation dose increasing, which can be explained by the energy distribution of interface traps. The interface trap energy density D IT (E IT ) as a function of the energy level E IT has been obtained by the least square optimization and shows the typical “U-shape”distribution. In detail, the rising humps at equivalent energy level in D IT (E IT ) curves are due to Si-H bonds that are broken down after irradiation, which corresponds to the increasing trap density. Moreover, it is found that the energy level of interface traps is redistributed after irradiation. The peak of humps in D IT (E IT ) curves occurs at the farther energy level with the increase of dose, which is similar to the equivalent energy level. It might arise from the shallow energy level of interface traps induced by radiation.

Torus Breakdown in a Uni Junction Memristor

Experimental study of a uni junction transistor (UJT) has enabled to show that this electronic component has the same features as the so-called “memristor”. So, we have used the memristor’s direct current (DC) [Formula: see text]–[Formula: see text] characteristic for modeling the UJT’s DC current–voltage characteristic. This has led us to confirm on the one hand, that the UJT is a memristor and, on the other hand, to propose a new four-dimensional autonomous dynamical system allowing to describe experimentally observed phenomena such as the transition from a limit cycle to torus breakdown.

Investigation of interface traps at Si/SiO2 interface of SOI pMOSFETs induced by Fowler–Nordheim tunneling stress using the DCIV method

The changes of interface trap density and distribution at the Si/SiO2 interface in partially depleted SOI MOSFETs were investigated by direct-current current–voltage (DCIV) method before and after Fowler–Nordheim tunnelling stress condition. The equivalent density and energy level of interface trap were obtained by combining the DCIV measurement results with the theoretical calculation using the least square method. It is concluded that the interface trap density increased as applying F–N stress due to the generation of Si dangling bond and the trapped charge at the Si/SiO2 interface, and the equivalent energy level of interface trap become close to the midgap with stress time increasing. In addition, interface trap density NIT as a function of their energy level EIT can be achieved, which were typical “U-shape” curves, and the interface trap density near midgap increases obviously as the F–N stress time increasing. An effective method is proposed to evaluate the interface state of SOI devices suffered electrical stress or other damages.

Effects of Thickness and Annealing on Optoelectronic Properties of Electrodeposited ZnS Thin Films for Photonic Device Applications

Thin layers of ZnS with thicknesses of 400 nm, 500 nm, and 700 nm have been electrodeposited on glass/fluorine-doped tin oxide substrates using a simple two-electrode setup under similar conditions. Structural characterization of the layers using x-ray diffraction (XRD) measurements showed that they were amorphous. The results of optical characterization carried out in the wavelength range of 315 nm to 800 nm using spectrophotometry revealed that the optical properties of the layers are strongly influenced by the film thickness as well as annealing conditions. The values of the refractive index, extinction coefficient, absorption coefficient, and dielectric constant obtained from normal-incidence transmittance spectra were generally lower after annealing, showing also the influence of postdeposition annealing on the deposited ZnS layers. Electrical characterization of the layers, using direct-current current–voltage measurement under dark conditions at room temperature, shows that the resistivity of the as-deposited and annealed layers is in the range of 1.4 × 104 Ω cm to 2.5 × 104 Ω cm and 2.5 × 104 Ω cm to 3.1 × 104 Ω cm, respectively. The results suggest that the optoelectronic properties can be tuned for particular applications by adjusting the thickness of the layers appropriately.

A DC current–voltage model for organic thin film transistor for circuit design

Organic integrated circuits based on organic thin film transistors (OTFT) are gaining more and more attention nowadays, the availability of accurate spice-like device model for OTFTs suitable for Electronic design automation (EDA) applications is particularly attractive. In this paper, we demonstrate the applicability of the accurate direct-current (DC) model for OTFTs suitable for EDA, the parameters in the unified model all can be extracted in a simple and direct way from the experimental measurements. Two types of top source and drain contact (TC) pentacene TFTs with different gate dielectrics are researched on, simulation results based Simulation Program with Integrated Circuit Emphasis (SPICE) are obtained with this model and parameters extracted, which show a very good agreement with measured curves in both transfer and output characteristics, so the DC model and the extracted parameters are verified.

Thin film deposition of metal oxides in resistance switching devices: electrode material dependence of resistance switching in manganite films

The electric-pulse-induced resistance switching in layered structures composed of polycrystalline Pr1−xCaxMnO3 (PCMO) sandwiched between Pt bottom electrode and top electrodes of various metals (metal/PCMO/Pt) was studied by direct current current–voltage (I-V) measurements and alternating current impedance spectroscopy. The I-V characteristics showed nonlinear, asymmetric, and hysteretic behavior in PCMO-based devices with top electrode of Al, Ni, and Ag, while no hysteretic behavior was observed in Au/PCMO/Pt devices. The PCMO-based devices with hysteretic I-V curves exhibited an electric-pulse-induced resistance switching between high and low resistance states. Impedance spectroscopy was employed to study the origin of the resistance switching. From comparison of the impedance spectra between the high and low resistance states, the resistance switching in the PCMO-based devices was mainly due to the resistance change in the interface between the film and the electrode. The electronic properties of the devices showed stronger correlation with the oxidation Gibbs free energy than with the work function of the electrode metal, which suggests that the interface impedance is due to an interfacial oxide layer of the electrode metal. The interface component observed by impedance spectroscopy in the Al/PCMO/Pt device might be due to Al oxide layer formed by oxidation of Al top electrode. It is considered that the interfacial oxide layer plays a dominant role in the bipolar resistance switching in manganite film-based devices.

Interface Defects and Negative Bias Temperature Instabilities in 4H-SiC PMOSFETs – A Combined DCIV/SDR Study

We study the structure of SiC/SiO2 interface defects and the effects of negative bias temperature stress (NBTS) in lateral 4H silicon carbide (SiC) PMOSFETs. Our devices have 90 nm thick SiO2 gate oxides thermally grown in N2O ambient at 1280°C on n-type SiC. We investigate virgin (unstressed) and stressed devices using two different techniques: (i) for electrical characterization, we use the direct-current current-voltage (DCIV) technique [1] which measures a recombination current via interface defects and charge pumping (CP) which measures the number of interface defects within a certain range of the SiC band gap; (ii) to study the structure of the defects, we use electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) [2]. The elevated temperature during NBTS is provided by in-situ heated test structures. This is the first EDMR study of p-doped SiC MOSFETs and the first negative bias temperature instability (NBTI) study of SiC MOSFETs using in-situ (on-chip) heating during stress.

Analysis of device parameters of Al/In2O3/p-Si Schottky diode

Thin film of indium oxide (In2O3) is deposited on p-silicon substrate using sol-gel spin technique. The sol-gel spin deposited film is very smooth with grain size and root mean square surface roughness of ~40nm and ~7.9nm, respectively. The device parameters of Al/In2O3/p-Si Schottky diode were investigated using direct current current-voltage (I-V) and impedance spectroscopy. The ideality factor and barrier height of the diode were determined to be 1.07+/-0.03 and 0.72+/-0.02eV, respectively. At higher voltages, the charge transport mechanism of the diode is controlled by a trap-charge limited conduction mechanism (TCLC). The series resistance profile of the diode was extracted to show the presence of the interface states changing with frequency.

Electrical Characterization of Electronic Materials Using FIB-assisted Nanomanipulators

Focused Ion Beam (FIB) systems have incorporated versatile nanomanipulators with inherent sophisticated machining capability to characterize the electrical properties of highly miniature components of electronic devices. Carbon fibers were chosen as a model system to test the applicability of nanomanipulators to microscale electronic materials, with special emphasis on the direct current current-voltage characterizations in terms of electrode configuration. The presence of contact resistance affects the electrical characterization. This resistance originates from either i) the so-called "spreading resistance" due to the geometrical constriction near the electrode - material interface or ii) resistive surface layers. An appropriate electrode strategy is proposed herein for the use of FIB-based manipulators.

Multiregion DCIV: A Sensitive Tool for Characterizing the $\hbox{Si/SiO}_{2}$ Interfaces in LDMOSFETs

By measuring the substrate current under the forward bias of source/drain-substrate junction, a multiregion direct current current-voltage (MR-DCIV) technique is used to characterize the interface trap density and location in shallow-trench-isolation (STI)-based laterally diffused metal-oxide-semiconductor devices. The interface traps in LDMOSFETs yielded sharp well-resolved peaks in MR-DCIV current spectra. The interface traps in STI region can be measured without inducing any potential damages on the gate oxide by this nondestructive characterization tool. This technique can provide not only across-wafer as-grown interface trap profile but also stress-induced defect information.

Electrical Correlation of Double-Diffused Metal–Oxide–Semiconductor Transistors Exposed to Gamma Photons, Protons, and Hot Carriers

Double-diffused metal-oxide-semiconductor n-channel power transistor devices were subjected to a high electric-field stress, gamma photons (60Co), and 10-MeV proton radiation, and were comparatively analyzed. The direct-current current-voltage and high-frequency capacitance-voltage techniques were used to characterize the two different regions under the gate oxide in this kind of devices. The Si-SiO2 interfaces at the channel side and at the drain side are characterized after thermal annealing. The correlation of the interface states with the trapped charge is a good quantitative tool to compare the effects from different degradation mechanisms. It is shown that, under given conditions, each kind of stress exhibits its own signature in the interface states versus the oxide charge plot.

Impurity Deionization Effects on Surface Recombination DC Current-Voltage Characteristics in MOS Transistors

Impurity deionization on the direct-current current-voltage characteristics from electron-hole recombination (R-DCIV) at SiO2/Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Read-Hall recombination kinetics and the Fermi distributions for electrons and holes. Insignificant distortion is observed over 90% of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory. This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range.