Direct Chip Attach Research Articles

Semiconductor-on-Polymer Wafer Level Chip Scale Packaging

Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semiconductor-on-Polymer (SoP) CSP and direct interconnect assembly is enabling flexible hybrid electronics and sensors today. SoP extends CSP package size reduction to less than 1.0X the die size. Semiconductor-on-Polymer (SoP) CSP results in ultra-thin semiconductor materials that are less than the thickness possible with bare die. SoP was initially introduced to the Flexible Electronics market; the technology has gained interest for conventional low profile, low-mid I/O, DCA type applications. Advanced SoP CSP is an ultra-thin packaging technology that is capable of complete die encapsulation using wafer level processing. Ultra-thin SoP CSP is new package technology. It is applied to fully characterized commercial devices, uses well know semiconductor materials and is generally “qualified by similarity” (QBS). Qualification for flexible applications supplement QBS with test procedures derived from established standards. The initial development of test methods and procedures was done with AFRL support in 2017. Initial reliability for the new flexibility tests will be presented. SoP CSP is undergoing further characterization for conventional applications. This includes testing that is typical of non-hermetic fully encapsulated parts. Flip-chip is the preferred method for assembly of SoP CSP. The ultra-thin package technology feature is fully utilized using Direct Interconnect (DI). Direct interconnect (DI) is defined as the die pad interconnect technology where the pad is connected directly to a board pad of equivalent size and spacing. Direct interconnect is common for low pad count devices such as RFID, NFC and other DCA applications. Direct interconnect is not typically considered for higher pin count devices…until now. This presentation shares the development of SoP CSP DI assembly that has progressed from 24 pin attachment to System-on-Chip assembly of DI pitch at <100um. The presentation also shows the technology roadmap for SoP CSP evolution. A case study of a SoP CSP application will be included with data from a fully assembled ultra-thin electronic system based on a SoP CSP SOC with total thickness less than 30um. The system includes on-board ultra-thin fully flexible sensors. A call to action will be made to embrace ultra-thin electronics. System Designers and IC Engineers will be encouraged to: BUILD! Create the vision for ultra-thin possibilities. Put electronics into places and things never before possible with, prototypes, testing, reporting, and introducing new thin concepts. Reliability Leaders will be encouraged to: TEST! Update test procedures and standards to include physical deformations and then report and challenge the industry to improve. Universities will be called to: CREATE! Generate new physics/models associated with deformations, develop interconnect innovations and advance new materials. In general, the presentation makes the case that hardware matters – Let's build some new technology.

Wafer Level Packaging to Address Future Direct Chip Attach Needs

This paper covers results from early pathfinding investigations of a wafer level package (WLP) technology that addresses future direct chip attach (DCA) needs. An overview of the WLP technology and pathfinding results covering key process flow evaluations and future challenges to apply the concept to DCA are presented. Proof-of-concept (POC) of 300mm wafer-level mold integrating with Cu bumps was demonstrated by investigating the mold thickness uniformity, wafer warpage, and solder joint reliability on the board. We conclude with a discussion of the key risk areas remaining challenges that includes the mold grinding thickness variance control, optimization of the material properties, and alternative low cost bumping technologies scalable less than 0.3mm pitch, and outline the next steps to continue data collection on the wafer warpage behavior, the die breakage strength, and the board level assembly process using a standard surface mount infrastructure in our pathfinding work.

Low Profile Silicon Interposer using Passive Integration (PICS)

Thanks to their 3D structure, the Silicon Capacitors offer drastic improvements in terms of performances compared to the commonly used ceramic and tantalum capacitors. They are also a smart way to reduce the application volume and increase the IP protection level. With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, IPDIA is offering for a large range of products, customized or standard components, a low cost packaging solution: the Wafer Level Chip Scale Packaging. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance. More than interacting on electrical functionality, WLCSP is interacting on mechanical and thermo mechanical properties with a higher miniaturization and a transfer directly on printed circuit boards without additional packaging steps. This paper presents the main characteristics of the 3D-IPD advanced technology emphasizing on its capability and advantages versus discrete components illustrated by different applications using ultra-thin IPD ( down to 60 μm ) and WLCSP.

Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits

Three-dimensional integrated circuit (3D IC) is a promising technology in today's IC packaging industry. Since the technology is in infancy stages, many aspects of this technology are still under heavy investigation. Reliability of through silicon via (TSV) interconnects and interlayer bondings between the silicon layers are issues that become more complicated in 3D ICs due to the complexity of the architecture and miniaturized interconnect. Optimizing design of these devices is essential in order to avoid short fatigue life of interconnects. This manuscript addresses the impact of design parameters such as die thickness, TSV diameter and pitch, and underfill thickness and properties on thermo-mechanical durability of direct chip attach (DCA) solder joints and TSV interconnects used in a 3D IC packages. A design was proposed where DCA is used to connect four layers of ICs and TSVs are used to connect the active layer of the dies to the second silicon layer. Solder joints, as small as [email protected] diameter, were used to attach silicon layers. A numerical experiment is designed to vary these factors at three levels using L9 orthogonal array. A 3-dimensional model of the package was built and model was solved under an accelerated thermal cycle loading. Solder is considered to be visco-plastic material and copper interconnects are assumed to follow bi-linear isotropic hardening behavior. Two continuum damage models; energy-partitioning (E-P) and Coffin-Manson; were used to assess the number of cycles to failure for solder joints and TSV copper interconnects, respectively. Minitab software was used to analyze the result of experiment and general linear model analysis of variance (GLMANOVA) was used to evaluate significance of each factor. The most influential factors on durability of solder interconnect are found to be underfill properties and height. However, the most influential factor on TSV durability is found to be TSV diameter. A non-linear response was observed for TSV pitch and diameter indicating that the optimum level is in the range selected. Location of failures was also found to depend on selected parameters and be a function of effective CTE. A simple analytical approach is presented to estimate the effective CTE for silicon layers containing TSVs. Effective CTE can be varied as one of the design parameters to achieve optimum design.

Direct Chip Attachment Packaging of a 2-D Thermal Flow Sensor

The design,fabrication and test of a direct chip attach packaged thermal flow sensor is given.The circular structure sensor measures the 2-D wind speed and direction by using calorimetric principle.The calorimetric flow sensor is fabricated by using two-step metal lift-off process on a ceramic slice.Then the KGD is glued to the backside of PCB board with package resin,and wire is bonded to the front side of PCB through a prefabricated hole.Finally,the chip is capsulated using thermal insulated package resin on the front side.The wind tunnel test of the packaged sensor chip is carried out.The sensor can detect 360°wind direction in a wind speed range of 6 m/s.

A chip-scale packaging technology for 60-GHz wireless chipsets

In this paper, we present a cost-effective chip-scale packaging solution for a 60-GHz industrial-scientific-medical band receiver (Rx) and transmitter (Tx) chipset capable of gigabit-per-second wireless communications. Envisioned applications of the packaged chipset include 1-3-Gb/s directional links using amplitude shift-keying or phase shift-keying modulation and 500-Mb/s-1-Gb/s omni-directional links using orthogonal frequency-division multiplexing modulation. This paper demonstrates the first fully package-integrated 60-GHz chipset including receive and transmit antennas in a cost-effective plastic package. A direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. The size of the DCA package is 7/spl times/11 mm/sup 2/ and the LGA package size is 6/spl times/13 mm/sup 2/. Optionally, the Tx and Rx chip can be packaged together with Tx and Rx antennas in a combined 13/spl times/13 mm/sup 2/ LGA transceiver package.

Double Bump Flip-Chip Assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.

Effects of hygrothermal aging on anisotropic conductive adhesive joints: experiments and theoretical analysis

Epoxy-based anisotropic conductive adhesive film (ACF) joints have been used in a number of interconnect applications, including direct chip attachment, i.e., chip on glass, chip on ceramics, etc. The ACF joints can be subjected to high relative humidity environment and are susceptible to moisture sorption, especially at elevated temperatures. The long-term hygrothermal aging will induce irreversible changes to epoxy resin systems due to susceptibility of the polymer resin to hydrolysis, oxidation, etc. In this study, the hygrothermal environment was used as an accelerator for the degradation of ACF joints in chip-on-glass (COG) assemblies, which were fabricated in the form of single-lap joints. The effects of aging on the epoxy-based ACF joints were characterized by shear tests and scanning electron microscopy (SEM) at accelerated aging times of 125, 250, 375 and 550 h. The results show that the strength of ACF joints decreases and the fracture mechanism gradually changes with hygrothermal aging. In order to further interpret the hygrothermally-induced degradation to the ACF joints, an ACF joint aging model with hygrothermal environment has been developed, introducing a dimensionless parameter A, which was obtained from the interfacial fracture energy.

Investigation and Minimization of Underfill Delamination in Flip Chip Packages

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (/spl psi/) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm//spl deg/C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm//spl deg/C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (/spl psi/), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.

Improvement of Board Level Reliability for &amp;mu;BGA Solder Joints Using Underfill

The underfilling μBGA as an alternative to direct chip attachment for high density packaging technologies have been developed. This paper discusses the thermomechanical and metallurgical effects of underfill material and the resulting improvement in board level reliability for underfilled μBGA assemblies. Finite element analysis (FEA) models were developed to predict the thermal fatigue life of the solder joints during thermal cycling tests for μBGA assemblies without and with underfill material. FEA predicted that the stress concentrated in the solder at the crevice between the solder ball and upper substrate was approximately 60 percent of the stress without underfill. Subsequently, the predicted fatigue life was as much as 10 times higher for the underfilled assemblies. The thermal fatigue failure of μBGA solder joints was also investigated experimentally using thermal cycle testing with subsequent solder joint analysis by scanning electron microscope (SEM) and energy dispersive X-ray (EDX). The experiments revealed that solder joint failure was caused by propagation of cracks that initiated in the solder at the upper interface between the solder ball and copper pad. The fatigue life of the underfilled assemblies was about 8 times that of the assemblies without underfill. The results showed that the underfill material can play an important role in improving board level reliability for μBGA solder joints in harsh environments.

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.

Flux-free direct chip attachment of solder-bump flip chip by Ar + H2 plasma treatment

The flux-free flip-chip bonding process using plasma treatment was investigated. The effect of plasma-process parameters on Sn oxide-etching characteristics was evaluated by Auger depth-profile analysis. The die-shear test was performed to evaluate the adhesion strength of an Sn-37mass%Pb and Sn-3.5mass%Ag solder-bump flip chip that was bonded after plasma treatment. The Ar + H2 plasma treatment reduced the thickness of the oxide layer on the Sn surface. The addition of H2 to the Ar plasma improved the oxide-etching characteristics. A low chamber pressure was more effective in oxide etching. The die-shear strength of the plasma-treated Sn-Pb and Sn-Ag solder flip chip was higher than that of the nontreated chip but lower than that of the fluxed chip. The difference in the die-shear strength between the plasma-treated specimen and the nontreated specimen increased with increasing bonding temperature. The plasma-treated flip chip fractured at the solder/top-surface metallurgy (TSM) interface at low bonding temperature, but at the solder/ under-bump metallurgy (UBM) interface at high bonding temperature.

Thermal stress analysis and design optimization of direct chip attach (DCA) and chip scale package (CSP) in flip chip technology

Underfill encapsulation is a technique used to reinforce the solder bumps between the chip and the substrate in flip chip technology. To determine the optimal geometrical parameters and material properties for the package and candidate underfill materials is an important strategy for improving the thermo-mechanical reliability of flip chip packages. In this study, a stress-function-based energy method was developed to evaluate the interfacial peel and shear stress distributions in multilayered packaging structures. The stress functions were expressed in terms of sine and cosine trigonometric series. Simple programming and short CPU time lead to accurate stress distributions. After comparisons with other proposed numerical methods and results, the developed model was then coupled with a Genetic Algorithm to optimize the design of the direct chip attach (DCA) and chip scale package (CSP) in order to diminish the interfacial stresses and the possibility of crack initiation. The results revealed that the maximum peel and shear stress values were productively decreased and their peaks moved toward the center after conducting the optimizations in both cases. Improved geometrical and material parameters of the flip chip package were determined.

Flip chip interconnect systems using copper wire stud bump and lead free solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly.

Underfilling fine pitch BGAs

Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty passing mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165/spl deg/C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results.

Water-assisted sub-critical crack growth along an interface between polyimide passivation and epoxy underfill

Direct chip attach (DCA) microelectronic packaging technology is gaining prominence due to its numerous advantages. Delamination (debonding) of the underfill epoxy/ polyimide passivation interface of a DCA during hydro-thermal reliability testing has always been one of the salient problems. We have studied the water-assisted sub-critical crack growth along this interface and our measurement offers important clues as to the origins of the poor hydro-thermal testing results for these interfaces. A modified asymmetric double cantilever beam (ADCB) testing technique has been used to measure the sub-critical crack growth velocity v at various relative humidities and temperatures as a function of the crack driving force (strain energy release rate) G*. The presence of a significant partial pressure of water pH2O produces a marked decrease (by up to a factor of 12) in the threshold G* for crack growth at measurable velocities. Above the threshold log v rises linearly with \(\sqrt {G^ * } \) but then enters a regime where the crack velocity (v=v*) is almost independent of \(\sqrt {G^ * } \). Finally, at the values of G* corresponding to rapid crack propagation in the absence of water, log v increases very rapidly with G*. By analogy to the classic work on water-assisted sub-critical crack growth in silica-based glasses, where very similar features are observed, we believe that the sub-critical crack growth along the polyimide-epoxy interface results from stress-assisted hydrolysis of primary covalent bonds, in our case ester bonds across the interface. The regime of \(\sqrt {G^ * } \) just above the threshold corresponds to a physicochemical situation where the water activity (pH2O) at the crack tip is the same as that of the gaseous environment. In the regime where v=v*≈ constant, the water activity at the crack tip is below that in the environment and the crack growth velocity is limited by the transport of water vapor to the bonds ahead of the crack tip. We develop a model of this crack growth following Wiederhorn 1967 that allows us to predict the sub-critical crack growth as a function of G* for arbitrary relative humidity and temperature conditions.

Electron microscopy study of interfacial reaction between eutectic SnPb and Cu/Ni(V)/Al thin film metallization

The wetting reaction between molten eutectic SnPb solder and a sputtered trilayer Cu/Ni(V)/Al thin film metallization was studied using cross-sectional transmission electron microscopy and scanning electron microscopy. Reaction temperatures were from 200 to 240 °C and reaction times ranged from 1 to 40 min. The initial reaction products were Cu6Sn5 and Cu3Sn. The latter transforms to the former after an annealing greater than 1 min at 220 °C. The Cu6Sn5 grains adhere well to the Ni(V) surface and no spalling of them was observed, even after 40 min at 220 °C. This surprising result indicates that the Cu/Ni(V)/Al or Cu6Sn5/Ni(V)/Al is a stable thin film metallization for low temperature eutectic SnPb solder direct chip attachment to organic substrates. Additionally, Kirkendall voids accompanied Cu3Sn formation, yet the voids disappear when the Cu3Sn transforms to Cu6Sn5.

Thermal Management in Direct Chip Attach Assemblies

Direct chip attach (DCA) packaging technologies are finding increasing application in electronics manufacturing particularly in telecommunications and consumer electronics. In these systems, bare die are interconnected directly to a printed circuit board. The two primary forms of DCA included chip on board (COB) where the die are attached face up and wirebonded to the substrate and flip chip on board (FCOB) where bumped die are interconnected active face down directly to low-cost organic substrates. In the current work, thermal management of four direct chip attach technologies is investigated. Experimental measurements are conducted exploring the junction-to-ambient thermal resistance and thermal dissipation paths for COB interconnection and three FCOB interconnect technologies including solder attach, anisotropic adhesive attach, and isotropic adhesive attach. A first-order chip-scale thermal design model is developed for flip chip assemblies exhibiting good agreement with the experimental measurements.

Recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications.

Coffin-Manson based fatigue analysis of underfilled DCAs

The continuing drive toward high-density, low-profile Integrated Circuit packaging has accelerated the spread of flip-chip technology to laminated substrates, creating direct chip attach (DCA) configurations. However, the substantial difference in the coefficients of thermal expansion (CTE) between the chip and the laminated substrates makes DCA configurations vulnerable to thermally-induced strains and the resulting solder joint fatigue. The reliability of flip-chip technology is dramatically improved by the gap between the chip and substrate with epoxy. The present effort is aimed at exploring the benefits of underfilling in DCA configurations. The thermo structural behavior of an underfilled DCA is evaluated using FEM and employing an axisymmetric model of a typical DCA structure. Numerical simulations are performed for different sets of underfill material properties. The results are used to determine the parametric sensitivity of the thermal strain in the solder joints and the axial and shear stresses in the underfill material and to define the desirable range of underfill material properties. These results together with the Coffin-Manson relation are used to predict the theoretical improvement in cycles to failure. The results suggest that to minimize fatigue failure, the CTE of an underfill material should match that of solder material and its Young's Modulus should be as high as the adhesion strength of the underfill allows.