Gate Dimensions Research Articles

Characteristics enhancement of a GaAs based heterostructure field-effect transistor with an electrophoretic deposition (EPD) surface treated gate structure

A Pt/AlGaAs/InGaAs/GaAs heterostructure field-effect transistor (HFET), prepared by an electrophoretic deposition (EPD) approach on gate Schottky contact region, is fabricated and studied. The EPD-based Pt-gates with three different molar ratios (ω0) are examined by scanning electron microscopy (SEM) image. Good Pt-gate coverage with effective reduction of thermal-induced defects at Pt/AlGaAs interface is achieved through a low temperature EPD approach. Experimentally, for a gate dimension of 1μm×100μm, a lower gate current of 1.9×10−2mA/mm, a higher turn-on voltage of 0.85V, a higher maximum drain saturation current of 319.3mA/mm, and a higher maximum extrinsic transconductance of 146.8mS/mm are obtained for an EPD-based HFET at 300K. Moreover, comparable microwave characteristics of an EPD-based HFET are demonstrated at different temperature ambiences. Therefore, based on the improved DC performance and inherent benefits of low cost, simple apparatus, flexible deposition on varied substrates, and adjustable alloy grain size, the proposed EPD approach shows the promise to fabricate high-performance electronic devices.

RF Operation of Hydrogen-Terminated Diamond Field Effect Transistors: A Comparative Study

Three sets of different gate-length field-effect transistors (250, 120, and 50 nm) have been defined on homoepitaxial hydrogen-terminated diamond with the 50-nm device being the smallest gate length diamond transistor fabricated to date. DC- and small-signal RF measurements were undertaken to compare the operation of these gate nodes. RF small-signal equivalent circuits were generated to contrast individual components and better understand the operation at various gate dimensions. Scaling the gate length to smaller dimensions leads to an increase in the cutoff frequency of these devices although parasitic elements are found to dominate at the shortest gate length of 50 nm, limiting the outstanding potential of these devices.

Hydrogen sensing characteristics of a Pt/AlGaN/GaN heterostructure field-effect transistor (HFET) prepared by sensitization, activation, and electroless plating (EP) approaches

A Pt/AlGaN/GaN heterostructure field-effect transistor (HFET), based on sensitization, activation, and electroless plating (EP) deposition approaches, is fabricated and studied. Utilizing the sensitization and activation processes, a dense and uniform Pd seed layer could be implanted on the AlGaN layer prior to Pt-gate formation. In addition, a dense Pt-gate morphology and excellent Schottky contact properties are obtained. This causes significant improvement in DC performance and thermal stabilities as compared with a thermal evaporation (TE)-based one. For a used gate dimension of 1×100μm2, the lower gate leakage current of 0.9 (8.4)nA, higher maximum extrinsic transconductance of 90.1 (52.1)mS/mm, and maximum drain saturation current of 325 (178)mA/mm are found for an EP Pt-gate HFET at 300 (600)K. Moreover, as a hydrogen gas sensor, the maximum drain current response (13.7%), high on/off ratio (8×105), and fast response (28s) and recovery (36s) time constants in 10,000, 50, and 5ppm H2/air gases are obtained at 400K, respectively. Therefore, the studied EP Pt-gate HFET shows promise for a high-performance electronic device and hydrogen gas sensing applications.

An enhancement-mode pseudomorphic high electron mobility transistor prepared by an Electroless Plating (EP) and a gate-sinking approaches

An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300–475K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525K), an EP-based PHEMT with threshold voltage shifting of +0.33V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1×100μm2, the studied EPHEMT presents low gate current of 6.5 (74.5)μA/mm, maximum extrinsic transconductance of 185.2 (150.6)mS/mm, maximum drain saturation current of 219.9 (98.8)mA/mm, and threshold voltage of 0.203 (0.196)V at 300 (475)K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.

(Invited) Development of 4 Inch and 6 Inch GaN-on-Si for High-Voltage Operation

GaN-based semiconductor devices have established their niches for both high power and high frequency operation due to their wide-bandgap, excellent transport properties, high critical field and high thermal stability, which cannot be matched by the Si-based electronics; great promises have been shown in a wide range of applications, such as highly efficient power amplifiers for mobile phone base-stations, commercial and military radar/satellite communications, advanced power transistors for power rectification with unprecedentedly low loses, power supply, motor drive, and other circuits in industrial equipment and electric/hybrid vehicles. As compared to existing Si power devices which have been and still remain the workhorse in the semiconductor industry, GaN power devices are around 20 times smaller in size and over 10 times efficient with much lower power loses. To realize the GaN performance in a cost-down platform and to continue using well-developed device fabrication technologies easily scalable to 6 inch and beyond in modern semiconductor industry, the integration of GaN-based electronics with Si platform is not only extremely emergent but also a win-win investment.The off-state breakdown behavior is one of the most important factors to examine how good the materials and epitaxial structures are for high power applications. The off-state drain current is mainly come from the space charge injection of electrons into the GaN buffer [1], as well as the Schottky gate reverse leakage current. Suppression of the off-state drain leakage current by using high quality insulating buffer layers is very essential for HEMTs based on GaN-on-Si (GOS) materials to improve both the off-state breakdown voltage and the ON/OFF ratio in power switching applications. To acquire a highly-resistive blocking buffer layer, thicker GaN epitaxial layers employing super-lattice (SL) structures and intentional dopants [2], such as carbon or iron, are usually utilized.AlGaN/GaN HEMT heterostructures were grown on (111) Si substrates by metal–organic chemical vapor deposition (MOCVD). The heterostructures consisted of a carbon doped GaN/AlN super-lattice and a carbon doped GaN buffer layer with a total thickness from 2.5 µm to 5 µm, followed by a 120-nm-thick undoped GaN channel layer, 18-21 nm of Al0.27Ga0.73N barrier, and 2-nm-thick GaN cap layer. The devices analyzed in this study were fabricated using our standard device fabrication technology for AlGaN/GaN HEMTs on Si. Ti/Al/Ni/Au multilayer was first deposited and annealed at 850°C in a nitrogen environment to form an Ohmic contact. Multiple doses and energies of nitrogen ion implantation were used for the device isolation and to maintain a planar geometry in the fabricated device to further reduce parasitic leakage current. Ni/Au based Schottky gate metallization was defined by using optical lithography followed by a standard lift-off process of the e-beam deposited metals. The gate dimension was 2 µm × 100 µm. The distances of gate-to-source (Lgs) was fixed at 2 µm while the gate-to-drain distance (Lgd) varied from 2 µm to 10 µm. The isolation characteristics were collected between two Ohmic metal pads with 5 µm spacing. A standard 250 µm × 150 µm Ohmic contact on the epitaxial side of the HEMT wafers and broad area Al contact on the back side of the substrates were also fabricated for vertical breakdown measurement.This presentation will review IQE’s development of the AlGaN/GaN HEMTs grown by MOCVD on low cost and large size (111) Si substrates scaling in diameter from 4 inch to 6 inch. Typical DC characteristics will be shown and compared between different epitaxial structures. For high voltage operation, the two-terminal isolation blocking voltage/leakage, vertical breakdown voltage, as well as three-terminal off-state breakdown voltage and off-state drain leakage current for AlGaN/GaN HEMTs grown on silicon substrates with different buffer thickness and different carbon doping concentration will be discussed. As shown in Figure 1, isolation blocking voltage is demonstrated to increase up to about 1000V at 1µA/mm on 5µm-spacing isolation pads and leakage current to decrease to about 5 nA/mm with increasing carbon doping concentration and buffer thickness. With the improved insulating buffer, high off-state breakdown voltage of 1.2 kV and low leakage current of 5×10-8A/mm are achieved.Figure 1. Isolation blocking voltage and leakage current measured between two isolation pads with 5µm spacing for a set of AlGaN/GaN HEMT structures grown on Si with different carbon doping concentration in buffer and different buffer thickness.1. M. Micovic, P. Hashimoto, H. Ming, I. Milosavljevic, J. Duvall, P. J. Willadsen, W. S. Wong, A. M. Conway, A. Kurdoghlian, P. W. Deelman, Jeong-S Moon, A. Schmitz, and M. J. Delaney, 2004. IEDM Technical Digest. IEEE International, 807-810 (2004).2. J. B. Webb, H. Tang, S. Rolfe, and J. A. Bardwell, Applied Physics Letters 75, 953-955 (1999).

Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget

Introduction Recently, lattice matched InAlN/AlN/GaN-on-silicon integration approach has attracted increasing attention due to the availability of high-quality GaN epiwafers with high throughput epitaxial growth on large area Si substrates for applications in power and RF devices with low power consumption [1-2]. Meanwhile, the development of gate-first process is useful to realize future self-aligned transistor structures. Conventional fabrication of InAlN/GaN high electron mobility transistors (HEMTs) or metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) involves gate-last process where high temperature (>800 oC) annealing is required to form Ti/Al/Ni/Au source and drain ohmic contacts [3]. This is a consequence of traditional gate metallization (e.g., Ni/Au) and gate dielectric not being able to survive such a high ohmic annealing temperature. Therefore, the development of good ohmic contacts with a low thermal annealing budget and thermally stable gate dielectric is required to realize the gate-first process integration for InAlN/GaN HEMTs/MOSHEMTs. In the present work, we report the fabrication and characterization of InAlN/GaN MOSHEMTs using a lift-off free, gate-first CMOS compatible process developed at low thermal budget. Experiment The lattice-matched In0.18Al0.82N/AlN/GaN-on-Si (111) HEMT structure used in this experiment is shown schematically in Fig. 1. The MOSHEMT fabrication using a gate-first process started from mesa isolation followed by 20 nm thick LaAlO3 (LAO) deposition using pulsed laser deposition (PLD) with a substrate temperature of 300 oC. Then, W was sputter deposited followed by gate definition using photolithography and dry etching method. Thereafter, Hf/Al/Ta layer was sputter deposited followed by rapid thermal annealing at 600 oC for 60 s in vacuum to form source and drain ohmic contacts. Results and Discussion The contact resistance and contact resistivity of Hf/Al/Ta ohmic contacts, as analyzed from linear transmission line method (LTLM), are found to ~0.60 Ω·mm and 6.7x10-6 Ω·cm2, respectively. At first, the thermal stability and reliability of the LAO gate dielectric upon 600 oC ohmic anneal in vacuum was optimized under several oxygen partial pressures during PLD. Comparison of capacitance-voltage and reverse gate leakage current characteristics of fabricated devices subject to different oxygen partial pressures in the range from 3.1×10-5 Torr to 5×10-3 Torr are shown in Figs. 2(a) and 2(b), respectively. It is found that LAO deposited under an oxygen partial pressure of 2.7×10-4 Torr exhibits the lowest gate leakage and highest accumulation capacitance, predominantly arisen by an increased dielectric permittivity (k~23.2). Finally, the gate-first CMOS compatible MOSHEMTs were fabricated by choosing the above optimized deposition condition for PLD (2.7×10-4 Torr @ 300 oC) of LAO. Devices having gate dimensions of W/L = 2×50/1 μm, gate-to-source distance of Lgs ~ 2 μm, gate-to-drain distance of Lgd ~ 6 μm, were used for DC output and transfer characterizations. The DC output and transfer characteristics are shown in Figs. 3 (a) and (b), respectively. The MOSHEMTs achieve a saturation drain current (Idsat) of 500 mA/mm at zero gate voltage, threshold voltage (Vth) of -12.6 V, maximum extrinsic transconductance (Gmax) of 44 mS/mm and on-resistance (Ron) of ~ 14 Ω/mm. Conclusion In conclusion, a gate-first CMOS compatible process for InAlN/AlN/GaN-on-Si MOSHEMTs fabrication has been developed. A low thermal budget (600 oC) for ohmic annealing is achieved through the use of Hf/Al/Ta source-drain contacts, thus allowing the fabrication of gate-first CMOS compatible MOSHEMTs using LaAlO3 as the gate dielectric as well as for device passivation purpose. The reasonable DC performance demonstrated (Idsat = 500 mA/mm, Gmax = 44 mS/mm, etc.) for a 1 μm gate length shows promising possibility for gate-first process integration of InAlN/GaN-on-Si MOSHEMTs.

Characterization of GaN MOSFETs on AlGaN/GaN Heterostructure With Variation in Channel Dimensions

GaN MOSFETs were developed on an AlGaN/GaN heterostructure in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure, and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. For devices with different types and sizes, discrepant field-effect mobilities were observed and the origins of the discrepancy were analyzed. One reason causing the discrepancy is the discrepancy of gate dimension between the design and fabrication. In devices with only mesa as the device isolation, the real channel width would be larger than the mesa width because a parallel channel might have formed in the isolation region just outside the device mesa. Boron ion implantation was found to be effective to cutoff the current path in the isolation region. Another reason causing the discrepancy is that the real channel length would be larger than the designed one owing to the lithography and gate dry recess process. To extract the correct mobility and effective channel length of the GaN MOSFET fabricated on AlGaN/GaN heterostructure with variation in the channel dimensions, several methods were proposed and compared basing on ring-type MOSFETs.

Performance Enhancement on an InGaP/InGaAs PHEMT With an Electrophoretic Deposition Gate Structure

Interesting pseudomorphic high electron mobility transistors using an electrophoretic deposition (EPD) approach are fabricated and studied. Due to the low-temperature deposited gate structure, the studied device exhibits enhanced performance with less thermal damages and improved Schottky contact properties by EPD approach. In comparison with a thermal evaporation (TE) device, the higher turn-on voltage, lower gate current, and lower interface state density are observed for the EPD device. For the gate dimension of 1 × 100 μm2 the EPD device shows the higher maximum drain saturation current of 242.2 (231.9) mA/mm and excellent maximum extrinsic transconductance of 151.6 (132.5) mS/mm at 300 (420) K. Besides, the EPD device presents a comparable RF performance as compared with the TE one. Due to the improved device performance and advantages of low cost, simple process, flexible deposition on varied substrate, and adjustable metal grain size, the reported EPD approach shows the promise for high-performance device applications.

High carrier mobility in suspended-channel graphene field effect transistors

A channel suspension method to fabricate high performance graphene field effect transistors (GFET) is presented in this paper. The balance is reached between gate efficiency and carrier mobility. A GFET with 15 μm × 15 μm gate dimension achieves a high normalized transconductance. Peak intrinsic carrier mobility is extracted to be 44 600 cm2v−1s−1. Suspension of the graphene channel is confirmed by AFM, SEM, and gate capacitance measurements. Unlike traditional substrate supported GFET, the proposed suspended-channel structure suppresses the influence of extrinsic scatterings and, meanwhile, maintains a certain gate controllability.

Effect of titanium contamination on oxygen atom recombination probability on plasma conditioned surfaces

As the tolerances in gate dimensions in integrated circuit manufacturing become ever more stringent, plasma process conditions must be very tightly controlled. The reactor chamber wall contamination is one of the major causes of process drifts and is therefore of prime importance. Here, the authors report a study of the role of Ti contamination on an oxidized silicon surface in affecting the heterogeneous recombination coefficient of O in an O2 inductively coupled plasma reactor. Recombination coefficients were measured, using the spinning wall method, with in-situ Auger electron spectroscopy (AES) for surface analysis during plasma operation. The O-atom recombination coefficient on a Ti-free surface was found to be 0.034. After using an evaporation source to deposit a small amount of Ti on the spinning wall (17% of the atomic composition obtained from AES), the O recombination coefficient decreased to 0.022. A possible mechanism is proposed in which Ti reacts with ≡Si-O• sites that are active in recombining O, forming ≡Ti-O• sites that are less efficient for O recombination.

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

Analysis of Random Telegraph Noise in 45-nm CMOS Using On-Chip Characterization System

An on-chip variability characterization system implemented in a 45-nm CMOS process is used for direct time-domain measurements of random telegraph noise (RTN) in small-area devices. A procedure for automated extraction of RTN parameters from large volumes of measured data is developed. Statistics for number of traps, NT, and single-trap amplitudes, ΔVth, are studied across device polarity, bias, and gate area. A Poisson distribution is used to model NT and a log-normal distribution is used to model ΔVth. The scaling of the two statistics across gate dimensions is discussed; the expected value of NT is shown to scale with (L - ΔL)-1, whereas the expected value of AVth is shown to scale with W-1(L - ΔL)-0.5. The two statistics are combined in a compact RTN probabilistic model representing the statistics of the overall ΔVth fluctuations because of RTN. This model is demonstrated to give accurate predictions of the tails of the measured RTN distributions at the 95th percentile level, which scale with W-1(L - ΔL)-1.5. A comparison between nMOS and pMOS devices shows that pMOS devices exhibit both a higher average number of traps and a larger average single-trap ΔVth amplitude, leading to a comparatively larger overall impact of RTN.

MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

The leakage current in standard MOSFET models (BSIM3/BSIM4) is typically modeled by drain–bulk and source–bulk diodes. This modeling method does not consider the impact of several parasitic bipolar devices. For the accurate modeling the impact of the following bipolar transistors has to be considered: a lateral bipolar transistor drain–bulk–source, a vertical bipolar transistor drain–bulk-substrate (only in isolated structures), and a vertical bipolar transistor source–bulk-substrate (only in isolated structures). For example, the drain or source leakage as a function of gate length cannot be modeled without the scalable parasitic bipolar devices. This contribution demonstrates the structure of a proposed macro model, implemented scalability (in most cases nonlinear), developed scaling equations, and physical explanation of this scaling.Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity. This model improvement solves not only leakage current scaling, but it also accounts for additional parasitic bipolar effects, such as current injection to the substrate.

New generation SiC based field effect transistor gas sensors

With the advances in SiC processing and high temperature packaging technology over the past few years as well as the accumulation of knowledge regarding the sensing characteristics of different gate metal/insulator material combinations for different gaseous substances SiC based field effect high temperature sensors are moving towards commercial maturity. The route towards commercialization has, however, also led to the necessity of making new considerations regarding the basic transducer design and operation. The focus of this paper is thus the investigation of some basic transducer related parameters’ influence on sensor device performance, e.g. sensitivity and long-term stability, and characteristics to exemplify the importance of taking design, processing and operation parameters into account when developing field effect sensor devices for commercial applications.Two different types of devices, enhancement and depletion type MISFET sensors, with different gate dimensions and two different gate metallisations, Pt and Ir, have been processed. I/V-characteristics have been obtained under exposure to various concentrations of H2, NH3, CO and O2 and different bias conditions and the influence of gate dimensions and bias conditions on the sensitivity and dynamic range investigated. The long-term stability has also been studied and compared between different devices and bias conditions for conceptually different gas compositions. The results show that the type of basic transducer device, its design and mode of operation has a large influence on sensor performance. Depletion type devices offer better possibilities for tuning of sensitivity and dynamic range as well as improved long-term stability properties, whereas enhancement type devices require much less control of the processing to ensure good repeatability and yield. Some results have also been verified for two possible applications of SiC based field effect sensors, ammonia slip monitoring for the control of SCR/SNCR and combustion control in domestic/district heating facilities.

A Study on Injection Molding Analysis and Structural Analysis with Truck Brake Pedal

Injection molding process one of the most important methods to produce plastic parts with high efficiency and low cost. Today, Injection molded parts have been increased dramatically the demand for high strength and quality applications. In this study, truck brake pedal is made of Cast iron and plastic materials to replace the frame for the optimization process that minimizes the runner and the gate dimension will determine the size and shape. Runner and gate dimensions of change based on availability of the product. I will discuss the injection molding. This report investigates that the optimum injection molding condition for minimum of runner and gate position. The FEM Simulation CAE tool, MOLDFLOW, is used for the analysis of injection molding process.

Caracterización eléctrica de nano-MOSFETs en tecnología SOI

En esta investigación se reporta sobre la extensa caracterización eléctrica realizada, con poca distorsión y mayor fiabilidad, a dispositivos MOSFET de tamaño nanométrico con arquitectura ultra delgada tipo Fully Depleted (FD) en tecnología Silicon-On-Insulator (SOI) para reducir los efectos de canal corto. Se comparan los parámetros de dispositivos tipo nMOS, con tamaño de compuerta 10x1 μm2, con dieléctrico convencional (SiON) y dieléctrico alternativo de alto κ (HfO2). Los parámetros que se extraen son: espesor equivalente de óxido (EOT), voltaje umbral (VT) en función del voltaje de cuerpo SOI (VB), transconductancia (gm), pico de transconductancia (gm,max) y su relación con la movilidad. El objetivo es encontrar si los métodos de caracterización eléctrica clásicos pueden ser aplicables para estos nuevos dispositivos superando los retos y dificultades físicas que impone la tecnología de construcción SOI y demostrar si su funcionamiento es como el de los MOSFET convencionales. Los dispositivos semiconductores analizados fueron provistos por el consorcio IMEC en Bélgica y han sido caracterizados en el nuevo laboratorio de nanoelectrónica de la Universidad San Francisco de Quito (USFQ) en Ecuador.

Modal Analysis and Design of a Vertically Movable Gate Field Effect Transistor (VMGFET) Proposed for Low-Frequency Sensing Applications

The objective of this study is to design and optimize a vertically movable gate field effect transistor (VMGFET) - suitable for low-frequency, high-sensitivity applications - with an emphasis on modal analysis of the suspended gate structure, optimization of mesh density within the employed finite element analysis software, and optimization of the moveable gate dimensions given its relationship with fabrication complexity and the structure’s resonant frequencies. The methods of design, optimization, and analysis were carried out with COMSOL Multiphysics 4.2a under the assumption of no damping with free vibrations. The results indicate optimal dimensions of the suspended gate structure - given constraints on size, resonance, and fabrication complexity - which suggest a beam thickness of 3 µm and a beam width of 15 µm, yielding an upper limit of input force frequencies near 2 kHz.

Modeling the geometric effects on programming characteristics for the TANOS device by developing a 3D self-consistent simulation

This paper reports a study on the programming characteristics of the TANOS (Ti gate – Al2O3–Si3N4–SiO2–Si) device using a 3-dimensional self-consistent numerical simulation. The STI (Shallow Trench Isolation) structure is considered in TANOS device simulation. The program characteristics are investigated in various active space and gate dimensions (width and channel length) using numerical simulation. It is found from the simulation that the STI effect becomes more important as the device size is scaled down. Since the STI effect is dependent on the channel width, length, and STI width, the framework of 3D simulation is crucial for scaled TANOS device design.

High-Temperature Performance of AlGaN/GaN MOSHEMT With $\hbox{SiO}_{2}$ Gate Insulator Fabricated on Si (111) Substrate

The dc operation of high-quality AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOSHEMTs) on Si (111) substrates, fabricated using $\hbox{SiO}_{2}$ as the gate insulator, is investigated for the first time as a function of ambient temperature $(T)$ . $I$ – $V$ and $C$ – $V$ characteristics of these depletion-mode devices are studied in the temperature range of 25–200 $^{\circ}\hbox{C}$ , and the results are compared to those of reference AlGaN/GaN HEMTs processed on the same wafer and of identical geometry. For devices with an 8- $\mu\hbox{m}$ drain-to-source separation and $\hbox{1} \times \hbox{2.5} \times \hbox{100} \mu \hbox{m}^{2}$ gate dimensions, the maximum output current density was about 730 mA/mm at $+$ 2 V gate bias for both types of transistors. The thermal behavior of the MOSHEMTs on Si was found to resemble that of devices grown on sapphire and silicon carbide with the gate leakage current exhibiting a rapid increase with $T$ but remaining below the levels seen in the reference HEMTs. The maximum drain current also showed a relatively smaller degradation at elevated temperatures as compared to previously published data.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique.