Digitally Controlled Delay Line Research Articles

Digital Background Calibration Techniques for 2GS/s 12bit Time-Interleaved Pipelined ADC

This paper presents digital background(BG) calibration techniques which are utilized to correct both inter-stage gain error (IGE) and inter-channel mismatches in a 12-bit 2GS/s 4-channel time-interleaved pipeline ADC. The inter-stage gain is mitigated by Least Mean Square (LMS) based calibration with a proposed Pseudo Noise (PN) codes injected into 1.5bit MDAC stages, which has neither input amplitude limitation nor comparator requirement. The inter-channel offset and gain mismatches are eliminated by Modified Moving Average (MMA) and LMS –based calibrations respectively. The inter-channel sampling time mismatch is estimated by correlation function and compensated by digital-controlled delay line. Simulation results in 40nm CMOS show that the presented calibration techniques improve the 2GS/s TI ADC SNDR from 46.2138dB to 6761.49dB 35dB and SFDR from 50.8150.09dB to 82.3574.04dB with a Nyquist input, consuming only 23.3mW power in a 184um*183um area.

A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

A digital phase-locked loop (DPLL) using the feedforward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm2. The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is −57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage.

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows

This brief proposes adaptive dither windows to calibrate bit weights in pipelined analog-to-digital converters (ADCs). It exploits the comparator meta-stability nature to construct dither windows, which avoids doubling the number of the comparators. The dither window size as defined by the sub-ADC comparator metastability region is tightly controlled and adapted to process-voltage-temperature (PVT) variations by adjusting the digitally controlled delay lines (DCDLs) against a capacitor-ratio reference. Besides, it cancels the voltage swing increment due to the dither windows, which relieves the design of the residue amplifier and saves the over-range margin of the stage. The proposed calibration technique is demonstrated by using a 12-bit pipelined ADC in a 40 nm CMOS process, and simulation results show that the window size is adjusted adaptively under PVT corners while the voltage swing increment is cancelled. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) are improved from 61.8 dB and 53 dB to 92 dB and 73.6 dB, respectively.

PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm2.

New Concept of Combined Microwave Delay Lines for Noise Radar-Based Remote Sensors.

Delay lines with a tunable length are used in a number of applications in the field of microwave techniques. The digitally-controlled analogue wideband delay line is particularly useful in noise radar applications as a precise detector of movement. In order to perform coherent reception in the noise radar, a delay line with a variable delay value is required. To address this issue, this paper comprises a new concept of a digitally-controlled delay line with a set of fine distance gates. In the paper, a solution for micro-movement detection is proposed, which is based on direct signal processing in the time domain with the use of a microwave analogue correlator. This concept assumes the use of a microwave analogue tapped delay line structure. It was found that the optimal solution for a noise radar with an analogue signal correlator is a combined delay line consisting of switched reference sections, a tapped delay line, and a precision phase shifter. The combined delay line presented in this paper is dedicated to serving as the adjustable reference delay for a noise radar intended for the detection of micro-movement. The paper contains the calculation results and delay line implementation for a given example. The new structure of the analogue tapped delay line with the calculation of optimal parameters is also presented. The precise detector of movement can be successfully used for the remote sensing of human vital signs (especially through-the-wall), e.g., breathing and heart beating, with the simultaneous determination of position.

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

This paper presents a 12-b, 1-GS/s ADC array, realized by time-interleaving four 250-MS/s pipelined SAR ADCs, with integrated on-chip reference voltage buffers. A reference ADC-based calibration algorithm treats static nonlinearity, gain, and offset errors in the array. Timing-skew errors between the sub-ADCs are distinguished from those of the gain mismatches by the assistance of an analog high-pass filter (HPF) for input slope information and subsequently corrected by digitally controlled delay lines (DCDLs). Directly driven off the on-chip 50- $\Omega $ termination resistors without any dedicated input buffer, the 65-nm CMOS prototype ADC array also employs a frequency-hopped, randomly-sampling scheme for the ref. ADC, eliminating the spectral effect of its interference to the main array. The core ADC consumes 31.5 mW and occupies an area of 0.27 mm2, including nine on-chip reference voltage buffers, the ref. ADC, and the HPF path. The measured peak signal to noise and distortion ratio of the array is 65.3 dB, and the measured spurious-free dynamic range is >70 dB from dc to 500 MHz at 1 GS/s with calibration. The prototype ADC chip achieves an figure of merit of 20.9 and 59.7 fJ/step (the latter is limited by the jitter of an off-chip clock source) for a low-frequency input and a Nyquist input, respectively.

A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process–voltage–temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of −249 dB favorably comparable with the state of the art.

Divider‐less SAR‐based ADDLL

A new all-digital delay-locked loop (ADDLL) using successive-approximation register (SAR) control scheme is presented. The proposed circuit architecture can effectively perform the per-bit acquisition within one clock cycle. Therefore, the divider for generating internal SAR clocks can be further removed to achieve fast-locking capability. Meanwhile, the harmonic-locking problem that often occurs in a wide range of operating frequencies is also eliminated. The test chip is designed and verified with CMOS 0.18 μm technology. The measured acquisition cycles for all operating frequencies (100–800 MHz) are constant as 11 when a 10-bit digital-controlled delay line is employed. The rms/peak-to-peak jitters at the highest and lowest frequencies are 0.775/5.73 and 1.08/8.27 ps, respectively. The chip core occupies an active area of 0.015 mm2 and consumes 9.4 mW at 800 MHz.

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS

This paper presents a power- and area-efficient 16-way time-interleaved (TI) analog-to-digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm CMOS. A voltage-time hybrid pipeline technique exploiting the comparator input-voltage-output-time dependency is reported to enhance the throughput of successive-approximation-register (SAR) ADCs. A reference-buffer-free capacitive digital-to-analog (CDAC) converter is utilized to mitigate the crosstalk problem in TI-ADCs. Timing mismatches between individual sub-ADCs are estimated with a reference-ADC dithering technique and corrected by digitally controlled delay lines (DCDL). The techniques collectively enabled a very compact design, obviating any input buffer or hierarchical sampling structures. The ADC core consumes 23 mW and occupies an area of 0.03 mm2. A signal-to-noise plus distortion ratio (SNDR) of 35 dB and a spurious-free dynamic range (SFDR) of 54 dB were measured for a 40-MHz input. For a Nyquist input, the prototype measured an SNDR of 29 dB and an SFDR of 41 dB with all timing mismatch spurs suppressed below −50 dBc after skew calibration.

Harmonic‐free and low cost delay‐locked loop with a 20–80% input duty cycle

A low-cost two-step delay locked loop (DLL) with a 20-80% input duty cycle is presented. For eliminating harmonic and zero-trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase-isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero-trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm 2 chip area. Simulation results show that the operation range of the proposed DLL is 0.3-1.6 GHz without the occurrence of harmonic and zero-trap locking, and the range of input duty cycle is 20-80%. The power consumption is 0.76 mW at 1.6 GHz.

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines

NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Existing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maximum working frequency. This paper proposes a novel glitch-free NAND-based DCDL that joins the advantages of previously proposed topologies: uses only a single flip-flop for each DE (reducing area and power) and has relaxed timing requirements (allowing easy integration in applications like SSCG). In the paper, the glitch-free operation of the proposed circuit is firstly demonstrated theoretically and then verified experimentally, with the help of an SSCG built using proposed DCDL and implemented in 28 nm CMOS. Simulation results show that proposed DCDL results in a more that 30 % reduction of the power dissipation and a >20 % reduction in area occupation with respect to double flip-flop DCDL, without any timing constraints penalty.

A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to reduce design complexity for the half-rate data recovery. In the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital phase tracking loop (DPTL) tunes retiming phase. For wide-range and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a wide-range digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a coarse frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.8–6.5 Gb/s data rates over 5 $^{\prime\prime}$ FR4 trace with $2^{31}-1$ PRBS pattern satisfying ${\text{BER}} . The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s.

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It can effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is within 17.5–23.5 or 17.5–32.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company’s (TSMC’s) 0.18- $\mu \text{m}$ CMOS cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.

High-Resolution Synthesizable Digitally-Controlled Delay Lines

Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation.

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds of clock cycles to achieve synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in a cell-based design flow. The proposed ADDLL circuit can acquire the phase of a clock signal from 60-MHz frequency to 1.2-GHz frequency. In this paper, the digitally controlled delay line (DCDL) is resettable such that our constant acquisition-cycle DLL algorithm can apply. This paper realizes the DCDL using lattice delay units in a linear manner, so the delay profile of our DCDL shows good linearity. On the other hand, the proposed ADDLL algorithm can effectively eliminate the harmonic lock. The ADDLL chip is implemented using the Artisan-TSMC-0.18- $\mu{\rm m}$ CMOS cell library. The measured power consumption of the chip is 16.2 mW at 1.2-GHz clock frequency and at 1.8 V supply voltage. The rms jitter is 1.63 ps and the peak-to-peak jitter is 12.8 ps. Both are measured at 1.2-GHz clock frequency.

An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter

An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) carefully. The proposed circuit is implemented in 0.18μm CMOS technology. Simulation results show that the proposed circuit performs well in various conditions in high speed data transmission applications.

A Segmented DCDL Based on Gate Delay and Phase Interpolation

The IC technology of adjustable delay is simply presented. Then aim at the engineering application forms a kind of segmented Digitally Controlled Delay Line (DCDL) which has overcame the tradeoff between adjustable delay resolution and dynamic range, benefited from small die area, high resolution and large adjustable range. Finally presented is the performance of the segmented DCDL which is fabricated by 0.18μm CMOS technology. From the test result, the DCDL’s resolution is 12ps and the dynamic range is 4ns.