A Segmented DCDL Based on Gate Delay and Phase Interpolation

Abstract

The IC technology of adjustable delay is simply presented. Then aim at the engineering application forms a kind of segmented Digitally Controlled Delay Line (DCDL) which has overcame the tradeoff between adjustable delay resolution and dynamic range, benefited from small die area, high resolution and large adjustable range. Finally presented is the performance of the segmented DCDL which is fabricated by 0.18μm CMOS technology. From the test result, the DCDL’s resolution is 12ps and the dynamic range is 4ns.