Abstract
A radiation-tolerant delay locked loop (DLL) for DDR2 memory interface is presented. The DLL adjusts clock phase by a coarse tuning loop using a multiplexer-based digitally controlled delay line (DCDL) and a fine tuning loop using a phase interpolator (PI). To protect the sensitive nodes from single event effect (SEE), thermometer coding with bubble correction and triple modular redundancy (TMR) techniques are adopted. In addition, a duty cycle corrector (DCC) with radiation-tolerant characteristic is developed. Designed in a 0.13 μm CMOS technology, the DLL achieves a phase resolution of 51.5 ps and a 10%–90% input duty cycle correction range. It consumes 15 mW of power under a 1.5 V supply voltage.
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