A low-power low-jitter DLL with a differential closed-loop duty cycle corrector

Abstract

A low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential closed-loop structure that corrects the input clock duty cycle from 10 to 90%. To have a wide range DLL, a low-power voltage control delay line using wide bandwidth and large tuning range delay cells is employed. The proposed DLL has been fabricated in a 0.13 μm CMOS process technology with an active Si area of 0.11 mm2. The measured results show the DLL exhibits a lock range of 0.1–1.2 GHz while the peak-to peak jitter and rms jitter are 7.3 and 1.2 ps at 1.2 GHz, respectively. The total power dissipated by the DLL is 4.8 mW with 1.2 V supply voltage at 1.2 GHz.