A reset-free anti-harmonic delay-locked loop using a cycle period detector

Abstract

This paper describes a new delay-locked loop (DLL) circuit that uses a replica delay line and a cycle period detector to solve the false lock problem in the conventional DLLs. The auxiliary loop in the proposed DLL monitors the lock state of the main loop by estimating the cycle period of the input clock and decides whether the main loop is in the coarse lock state or not. The auxiliary loop does not require an external reset or a start-up signal for the coarse lock operation, which is performed in the background without affecting the fine lock operation of the main loop. The proposed DLL is useful in the applications such as wide range DLLs and multiphase clock generators. The proposed DLL was implemented in 0.25-/spl mu/m mixed-mode CMOS technology and its operating frequency ranges from 30 to 200 MHz. Its cycle-to-cycle rms jitter is 12.8 ps at 133 MHz, and it dissipates 30 mW at 2.5 V.