Digital Signal Processing Operations Research Articles

Fission counter array for pulse-mode measurements of high-flux and high-energy neutrons

This manuscript describes a neutron counting system based on cylindrical fission counters that can monitor neutron activity for high-energy neutron flux above 10 MeV under electrically noisy environments with intense gamma rays. Miniature fission counters with depleted uranium as sensitive material and modular electronics were built for digital signal processing and high-countrate operation. The counters are 9.5 mm in diameter and 71.1 mm in active length. The author presents the results of Monte Carlo simulations of the fission-counter response for selected neutron sources and energies based on ENDF7.1, JENDL-5, and TENDL-2021 nuclear data libraries from 1 meV to 200 MeV. For a white neutron beam (E‾ = 16.36 MeV) that irradiates the front face of a counter, the intrinsic efficiency is evaluated to be (2.24 ± 0.02) × 10−5 counts/n, while the efficiency of the counter in the array appears to increase by at most 6.7%.

A review of differentiable digital signal processing for music and speech synthesis

The term “differentiable digital signal processing” describes a family of techniques in which loss function gradients are backpropagated through digital signal processors, facilitating their integration into neural networks. This article surveys the literature on differentiable audio signal processing, focusing on its use in music and speech synthesis. We catalogue applications to tasks including music performance rendering, sound matching, and voice transformation, discussing the motivations for and implications of the use of this methodology. This is accompanied by an overview of digital signal processing operations that have been implemented differentiably, which is further supported by a web book containing practical advice on differentiable synthesiser programming (https://intro2ddsp.github.io/). Finally, we highlight open challenges, including optimisation pathologies, robustness to real-world conditions, and design trade-offs, and discuss directions for future research.

On the optimum multicarrier performance with memoryless nonlinearities

One of the major problems associated with multicarrier signals is their high envelope fluctuations that lead to implementation difficulties. Therefore, multicarrier signals are usually submitted to nonlinear operations such as clipping to simplify the power amplification, DAC (Digital-to-Analog Conversion) and other digital signal processing operations. However, these nonlinear operations lead to nonlinear noise that usually is associated with performance degradation. Recently, it was shown that the nonlinear distortion associated to bandpass memoryless nonlinear devices not only does not necessarily means performance degradation, but can even lead to performance gains. In this paper we study the impact of non-bandpass memoryless nonlinearities on the performance of multicarrier signals. We consider both nonlinear devices operating on the real-valued multicarrier signals as well as Cartesian nonlinear devices (also denoted as I-Q nonlinearities) operating separately on the real and imaginary parts of the complex envelope of multicarrier signals. We present a theoretical analysis of the potential performance improvements associated with the optimum detection of multicarrier signals, by deriving accurate theoretical expressions for both the average asymptotic gains in ideal AWGN (Additive White Gaussian Noise) channels and the asymptotic gain distribution for frequency-selective channels with multipath Rayleigh fading.

Design and implementation of hybrid logic based MAC unit using 45 nm technology

Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on delay, necessitating the accomplishment of DSP operations within a predetermined timeframe, hence rendering deferred processing not feasible. Therefore, digital signal processing (DSP) necessitates a multiplier and accumulator (MAC) unit that exhibits fast speed, high throughput, and low power consumption. This research aims to develop and execute a low-power MAC unit utilising a hybrid logic technique to achieve power efficiency. A MAC unit has been purposefully designed with suitable geometries to provide optimised power, area, and delay characteristics. Estimating the delay in the MAC unit depends upon data flow analysis between the MAC blocks, explicitly focusing on low-power concerns. The developed hybrid adder cell possesses several advantageous characteristics, including a high operational speed, low power consumption, minimal transistor count. The MAC architecture uses a 45 nm CMOS technology with the Mentor Graphics tool. This research additionally examines different designs of multipliers and adders that are well-suited for the execution of high throughput signal processing while simultaneously achieving low power consumption. The registers in the MAC have been implemented in GDI logic using Multi Bit Flip flops technique to achieve low power operation. The entire MAC circuitry operates on a voltage supply of 1 V. The hybrid logic MAC architecture that has been developed demonstrates a significant decrease in area consumption, amounting to a reduction of 68 % when compared to the typical CMOS logic design. Hybrid logic demonstrates a power consumption that is 92 % better compared to CMOS logic.

FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

ABSTRACT Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%).

A Multi-Channel Borehole Strain Measurement and Acquisition System Based on FPGA.

In this study, an FPGA(Field Programmable Gate Array)-based borehole strain measurement system was designed that makes extensive use of digital signal processing operations to replace analog circuits. Through the formidable operational capability of FPGA, the sampled data were filtered and denoised to improve the signal-to-noise ratios. Then, with the goal of not reducing observational accuracy, the signal amplification circuit was removed, the excitation voltage was reduced, and the dynamic range of the primary adjustments was expanded to 130 dB. The system's online compilation function made it more flexible to changes in measurement parameters, allowing it to adapt to various needs. In addition, the efficiency of the equipment use was enhanced. The actual observational results showed that this study's FPGA-based borehole strain measurement system had a voltage resolution higher than 1 μV. Clear solid tides were successfully recorded in low-frequency bands, and seismic wave strain was accurately recorded in high-frequency bands. The arrival times and seismic phases of the seismic waves S and P were clearly recorded, which met the requirements for geophysical field deformation observations. Therefore, the system proposed in this study is of major significance for future analyses of geophysical and crust deformation observations.

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

AbstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform

Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively.

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware acceleration of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production of special purpose digital signal processing (DSP) devices. The implementation of DSP algorithms is variative in nature and affects important indicators of a produced device, such as the accuracy of the numerical solution, performance, structural/functional complexity, etc. The architectural features of the FPGA can be used for choosing an effective DSP algorithm in the form of solving the multicriteria discrete optimization problem. This paper analyzes and selects an effective algorithm for calculating the integer square root, which is one of the most frequently used digital signal processing operations. A behavioral model based on a non-restoring algorithm is presented. The SystemVerilog description of the module for calculating the square root, presented in the form of a universal configurable IP core, has been developed and synthesized. The configuration allows one to change the width of the input data bus and select the serial or parallel processing mode for scalar or vector data. The results of testing and comparison of the obtained characteristics with the corresponding Xilinx Cordic IP core are presented. The field test of the proposed IP core implemented in the Xilinx FPGA SOC xc7z045ffg900-2 has demonstrated the gain in the maximum system frequency at 174 MHz in the sequential mode with a 48-bit input bus and 169 MHz in the pipelined mode at a reduction of both the structural complexity and the number of used FPGA internal resources in comparison with the Xilinx Cordic IP core.

Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications

Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

An optimization approach to the development of parallel algorithms for digital signal processing operations

The paper studies the optimization possibilities of an approach which made it possible to develop a formal tool, i.e. a model of computation organization for digital signal processing (DSP) operations and operations structurally similar to them. The resulting formal tool describes the inter-nal parameterized structure of operations and generates adaptive algorithms that can adjust to dif-ferent conditions of parallel computation. The developed approach to the construction of such algo-rithms endows them with extended functionality, which ensures the implementation of the follow-ing capabilities: changes in the parameters of algorithm structures; synthesis of their variety; opti-mization of variants of computation organization. Due to the variety of this functionality, several directions are identified for implementing this optimization. A general description of the optimiza-tion approach to the reasonable choice of the best variant of computation organization under the given conditions of their implementation is given. We consider a scheme of actions aimed at com-putation optimization and enabling you to develop various classes of parameterized parallel algo-rithms within the framework of the approach proposed.

Signal Processing-Based Deep Learning for Blind Symbol Decoding and Modulation Classification

Blindly decoding a signal requires estimating its unknown transmit parameters, compensating for the wireless channel impairments, and identifying the modulation type. While deep learning can solve complex problems, digital signal processing (DSP) is interpretable and can be more computationally efficient. To combine both, we propose the dual path network (DPN). It consists of a signal path of DSP operations that recover the signal, and a feature path of neural networks that estimate the unknown transmit parameters. By interconnecting the paths over several recovery stages, later stages benefit from the recovered signals and reuse all the previously extracted features. The proposed design is demonstrated to provide 5% improvement in modulation classification compared to alternative designs lacking either feature sharing or access to recovered signals. The estimation results of DPN along with its blind decoding performance are shown to outperform a blind signal processing algorithm for BPSK and QPSK on a simulated dataset. An over-the-air software-defined-radio capture was used to verify DPN results at high SNRs. DPN design can process variable length inputs and is shown to outperform relying on fixed length inputs with prediction averaging on longer signals by up to 15% in modulation classification.

Distributed fiber sensor network using telecom cables as sensing media: technology advancements and applications [Invited

Distributed fiber optic sensing (DFOS) is a rapidly evolving field that allows the existing optical fiber infrastructure for telecommunications to be reused for wide-area sensing. Using the backscattering mechanisms of glass—which includes Rayleigh, Brillouin, and Raman backscatter—it is possible to realize distributed vibration and temperature sensors with good sensitivity at every fiber position, and spatial resolution is determined by the bandwidth of the interrogation signal. In this paper, we will review the main technologies in currently deployed DFOS. We review the digital signal processing operations that are performed to extract the sensing parameters of interest. We report recent distributed vibration sensing, distributed acoustic sensing, and distributed temperature sensing field trial results over an existing network with reconfigurable add/drop multiplexers carrying live telecom traffic, showing that the network is capable of simultaneous traffic and temperature monitoring. We report Brillouin optical time-domain reflectometry experimental results for monitoring static strain on aerial fiber cables suspended on utility poles. Finally, we demonstrate an example of network modification to make passive optical networks compatible with DFOS by adding reflective semiconductor optical amplifiers at optical network units.

Performance Analysis of Adiabatic Vedic Multipliers

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

Parameter Estimation and Classification via Supervised Learning in the Wireless Physical Layer

Emerging wireless networks possess the potential to achieve levels of connectivity and Quality-of-Service (QoS) that are orders of magnitude higher than today’s networks. Realizing the potential of these networks will require flexible, low cost, and accurate Digital Signal Processing (DSP). Supervised Learning (SL) models employing unknown parameter estimation and classification techniques have experienced widespread use in physical (PHY) layer wireless communication systems since they can achieve low costs via inexpensive forward-pass computations, attain flexible operations due to trainable parameters, and yield accurate results based on the universal approximator attribute. In this tutorial paper, we present a methodical explanation of how SL can be applied to unknown parameter estimation and classification across several different PHY layer components of a wireless communications system. Additionally, via a survey and comparison of popular methods, this paper provides insights on how to perform weight training, weight initialization, loss function regularization, data pre-processing, input feature design, ensemble training, and hyper-parameter validation. In our review of state-of-the-art works, we found significant use of SL algorithms in the following PHY layer applications: Dynamic Spectrum Access (DSA), channel corrections, Automatic Gain Control (AGC), Multiple Input Multiple Output (MIMO) control, Analog to Digital (ADC) conversion, and Automatic Coding and Modulation (ACM). The overarching goal of this survey and tutorial paper is to assist the reader in understanding the motivation and methodologies associated with various SL algorithms applied to PHY layer DSP operations, as well as to provide the reader with the necessary tools and techniques needed for addressing open challenges to be experienced by future wireless networks.

REVERSE ENGINEERING OF NONLINEAR SYSTEMS USING ANALYTICAL NETWORKS

A method for the synthesis of numerical models based on analytical networks for nonlinear systems ofincreased complexity using their known input and output signals taken synchronously is proposed. The functioning of the proposed analytical networks is based on the use of a modified genetic algorithm and a library of blocks of constant functionality. Genotype structure and mutation algorithms are proposed for describing an analyticalnetwork. In addition, methods for modeling complex non-linear systems using the Volterra, Wiener-Hammerstein series, adaptive filters, non-linear model of an autoregressive moving average with exogenous inputs, neural networks and genetic algorithms are considered, and the main problems that arise when using these models are identified. Apractical example of the possibility of using the analytical network is shown on the example of the resynthesis of asound synthesizer. A typical diagram of such a synthesizer is described. A possible scheme of a re-synthesized system based on an analytical network that is functionally as similar as possible to desired system is considered. The possibility of automatically constructing a numerical model of the reaction of a nonlinear mechanical system to inputdisturbances using known input and output signals recorded synchronously is shown. The main difficulties of theresynthesis of complex systems for sound reproduction are considered - the influence of psychoacoustic phenomena on the perception of synthesis results and the need to ensure high fidelity for obtaining adequate results are shown.The structure of typical blocks of the analytical network is proposed, which should include typical conversions used in digital signal processing, arithmetic and logical operations, correlation and comparison blocks, hysteresis components, and in addition, typical possible standard blocks of a system that undergoes resynthesis.

Performance of momentum-based frequency-domain MIMO equalizer in the presence of feedback delay.

A frequency-domain multiple-input multiple-output (FD-MIMO) equalizer employing a momentum-based gradient descent update algorithm is proposed for polarization multiplexing coherent receivers. Its performance in operation with dynamically varying optical channels is investigated and the impact of filter update delays, arising from the latency of the fast Fourier transforms (FFTs) and other digital signal processing (DSP) operations in the feedback loop, is assessed. We show that the proposed momentum-based gradient descent algorithm used to control the equalizer response has significantly greater tolerance to feedback delay than the conventional gradient descent algorithm. We considered a 92 Gbaud dual-polarization 64 QAM receiver, with DSP operating at two samples per symbol, and with the equalizer operating on blocks of 512 and 1024 samples (i.e., 512/1024-point FFT). We found that at an optical signal-to-noise power ratio (OSNR) of 35 dB, the momentum-based gradient descent algorithm can successfully track state-of-polarization (SOP) rotation at frequencies of up to 50 kHz and with filter update delays of up to 14 blocks (39 ns). In comparison, using the conventional gradient descent algorithm in an otherwise identical receiver, the equalizer performance starts to deteriorate at SOP rotation frequencies above 20 kHz.

Manipulation of Terahertz Wave Based on Three-Layer Transmissive Pancharatnam-Berry Phase Metasurface

In order to improve the transmitted efficiency of metasurfaces, the three-layer unit cell structure with coupling characteristics between layers was proposed. Using these Pancharatnam-Berry phase element particles with three-layer structure, we constructed encoded metasurfaces with different sequences to control the transmitted scattered waves. However, the manipulation of continuous transmission angle requires the continuous change of encoding metasurface period. Since the size of encoding particles in the coded metasurfaces cannot be designed to be infinitesimally small, it is impossible to obtain the continuously changing period of coded metasurfaces. In order to obtain the continuous manipulation of transmission scattering angles, we introduced the principle of Fourier convolution operation in digital signal processing on encoding metasurface sequences. By performing the addition and subtraction operation between two different encoding metasurface sequences, a new encoding metasurface sequence can be obtained with different scattering angle. The transmission scattering angles can be obtained continuously, and the terahertz wave can be manipulated freely. Moreover, by using the proposed three-layer highly efficient Pancharatnam-Berry phase encoding meta-atoms, these coded particles with different rotation angles can be precisely arranged to build the generators of the orbital angular momentum beam with different topological charges.

Design and Analysis of 32 bit R evers e C onverter based on low power Parallel Prefix A dder

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

Vibroacoustic analysis of marine engine supplied with mixture of fuels

The main purpose of this paper is to obtain the differences in the vibrations of engine (Doosan MDT196TI) which was powered using two different fuel mixtures – liquefied natural gas with diesel pilot and diesel only. LNG and diesel oil differ in combustion temperature, density, and cetane number; the combustion process of various fuels proceeds differently, so it has an impact on the generated vibroacoustic vibrations (vibrations have a direct impact on the degree of machine degradation). In the research, the diagnostic system is based on piezoelectric accelerometers and Digital Signal Processing operations (windowing, Fast Fourier Transform). In the conclusions section the obtained results are analysed, indicating how the tested fuels have an effect on vibrations.