Performance Analysis of Adiabatic Vedic Multipliers

Srilakshmi Kaza, Et Al

doi:10.17762/turcomat.v12i5.2039

Abstract

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

Highlights

In the fields of image processing and Digital Signal Processing (DSP) multipliers plays a crucial role
A 4x4 vedic multiplier is implemented with FinFET based Modified PFAL (MPFAL) logic using Brent-Kung Adder (BKA) is presented in this paper
The different device parameters selected are as follows, Channel Length (L) as45nm, Fin Thickness (Tfin) as 15nm, Height of the Fin (Hfin) as 30nm, Oxide Thickness (Tox) = 1nm, and threshold voltage of 0.4V

Summary

Introduction

In the fields of image processing and DSP multipliers plays a crucial role. The fundamental algorithm like FFT requires more number of addition and multiplication operations. Among which a multiplier circuit makes use of vedic principles is found to be a faster one. The most attractive design technique at the circuit level is energy recovery logic [7,8] which make use of thermodynamic principle. The use of FinFET as an alternative to CMOS further improves the energy recovery of the adiabatic logic. The performance comparison of different adiabatic circuits based on FinFET is analyzed with a Brent-Kung Adder as a test module[11]. A 4x4 vedic multiplier is implemented with FinFET based MPFAL logic using Brent-Kung Adder (BKA) is presented in this paper. In our earlier work Vedic multiplier is implemented with FinFET based ECRL logic using (RCA) [12].

Adiabatic Logic

Simulation Results

Conclusion