Digital Signal Processor Core Research Articles

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.

Multichannel Baseband Processor for Wideband CDMA

The system architecture of the cellular base station modem engine (CBME) is described. The CBME is a single-chip multichannel transceiver capable of processing and demodulating signals from multiple users simultaneously. It is optimized to process different classes of code-division multiple-access (CDMA) signals. The paper will show that through key functional system partitioning, tightly coupled small digital signal processing cores, and time-sliced reuse architecture, CBME is able to achieve a high degree of algorithmic flexibility while maintaining efficiency. The paper will also highlight the implementation and verification aspects of the CBME chip design. In this paper, wideband CDMA is used as an example to demonstrate the architecture concept.

Perception SoC Based on an Ultrasonic Array of Sensors: Efficient DSP Core Implementation and Subsequent Experimental Results

We are concerned with the design, implementation, and validation of a perception SoC based on an ultrasonic array of sensors. The proposed SoC is dedicated to ultrasonic echography applications. A rapid prototyping platform is used to implement and validate the new architecture of the digital signal processing (DSP) core. The proposed DSP core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering, and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a angle of view span. The design uses a minimum size lookup memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.

A scalable instruction buffer and align unit for xDSPcore

Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core.

Low-Power Embedded DSP Core for Communication Systems

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterizedb data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 µm SPQM and 0.25 µm 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a 16 × 16 version is 100 MHz (0.35 µm) and 140 MHz (0.25 µm).

Assigning service requests in Voice-over-Internet gateway multiprocessors

New and proposed communication systems are entirely digital, including Voice over Internet Protocol tasks as well as traditional data packets, fax, etc. Numerous digital signal processing (DSP) algorithms are available to encode and decode these signals, each having different requirements for data memory, program memory, and processor speed. A DSP multiprocessor having numerous DSP cores receives a stream of requests for encoding and decoding tasks. A service request is “blocked” if no DSP core can handle the task when it arrives. We present algorithms for assigning DSP tasks to cores in order to minimize the number of blocked tasks. This is similar to an online bin-packing problem with the important difference that the program memory can be shared between simultaneous service requests for the same DSP algorithm. Since bin-packing is known to be NP-complete, we develop fast heuristic online methods for this problem.

Fault-coverage analysis techniques of crosstalk in chip interconnects

This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing. Based on a covering relationship we distinguish between transition tests in detecting crosstalk defects and develop an abstract crosstalk fault model for chip interconnects. With this fault model and the covering relationship, we develop a fast and efficient method to estimate the fault coverage of any general test set. We also develop a simulation-based technique to calculate the probability of occurrence of the defects corresponding to each fault, which enables the fault-coverage analysis technique to produce accurate estimates of the actual crosstalk defect coverage of a given test set. The crosstalk test and fault properties, as well as the accuracy of the proposed crosstalk coverage analysis techniques, have been validated through extensive simulation experiments. The experiments also demonstrate that the proposed crosstalk techniques are orders of magnitude faster than the alternative method of SPICE-level simulation. Finally, we demonstrate the practical applicability of the proposed fault-coverage analysis technique by using it to evaluate the crosstalk fault coverage of logic BIST tests for the system-level interconnects and buses in a digital signal processor core.

A 600-MHz VLIW DSP

A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 719 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an eight-way VLIW DSP core, a two-level memory system, and an I/O bandwidth of 2.4 GB/s. The chip integrates a c64X DSP core with Viterbi and turbo decoders. Architectural and circuit design approaches to achieve high performance and low power using a semi-custom standard cell methodology, while maintaining backward compatibility, are described. The chip is implemented in a 0.13-/spl mu/m CMOS process with six layers of copper interconnect.

Sorting networks using L/sub p/ mean comparators for signal processing applications

Digital implementations of sorting networks that rely on a digital signal processor core are not as efficient as their analog counterparts. This paper builds on the L/sub p/ comparators for which efficient analog implementations exist that employ operational amplifiers. From a statistical point of view, L/sub p/ comparators are based on nonlinear means. Their probability density function and the first- and second-order moments are derived for independent uniformly distributed inputs. L/sub p/ comparators provide estimates of the minimum and maximum of their inputs. A proper approach to compensate for the estimation errors is proposed. Applications of the L/sub p/ comparators in odd-even transposition networks, median approximation networks, and min/max networks are presented.

VLIW DSP for mobile applications

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented.

CBP and ART image reconstruction algorithms on media and DSP processors

Computed Tomography (CT) image reconstruction algorithms such as convolution back-projection (CBP) and algebraic reconstruction technique (ART) are highly compute-intensive for today's single processor systems. In this work, we investigate the suitability of TM-1000 media processor and Analog Device's ADSP 21160 as a compute engine for the execution of image reconstruction algorithms. Philips Trimedia TM-1000, a very large instruction word (VLIW) processor, is a high performance media processor optimized for real-time processing of audio, video, graphifcs, and communication data streams. TM-1000 has a high performance digital signal processor (DSP) core, supported by multiple functional units. The DSP core and the functional blocks operate in parallel, driven by a mix of RISC, multimedia, SIMD-type DSP and floating point instructions. A typical DSP such as Analog Device's ADSP 21160 is based on super harvard architecture (SHARC) and is an optimized processor for digital signal processing applications. It has two sets of computation units. Each computation unit comprises of three functional blocks namely, arithmetic and logic unit (ALU), multiplier and shifter unit. ADSP 21160 supports single instruction multiple data (SIMD) computation model to handle dual computation units. Both sets of computation units operate concurrently. We compare the performance of TM-1000 media processor and ADSP 21160 DSP processor to execute the image reconstruction algorithms by comparing the execution time of CBP and ART algorithms on them. The image reconstruction algorithms normally break down to a repetitive multiply-accumulate operation (MAC). All DSP processors support single-cycle MAC and zero-overhead loop instructions. The media processors normally do not support single-cycle MAC instruction and zero-overhead loop functionality. However, media processors are equipped with multiple functional units that perform multiple operations in a single instruction time. A DSP processor is expected to execute image reconstruction algorithms much faster than a multimedia processor. However, the experimental results show that the execution time on DSP and media processor are more or less same when 16-bit representation is used for data. When floating point data is used for implementation, DSP processor has an edge. ADSP 21160 gives same execution time for both floating point and 16-bit fixed point data. But, the execution time almost doubles when data is in floating point format on the media processor, compared to a 16-bit implementation. This can be attributed to the fact that TM-1000 processes two sets of operands in a single instruction time when data is in 16-bit format. The executable code for ADSP 21160 was generated from an optimized assembly language program whereas the executable code for TM-1000 was generated from an optimized ‘C’ with a few custom operations.

A 3-V GSM baseband transmitter

A dual-channel baseband transmitter has been designed for global system for mobile communications (GSM) cellular phone application. It has been fabricated in a 0.35-/spl mu/m digital CMOS process as part of a single-chip solution for baseband processing. Each channel consists of a switched-capacitor digital-to-analog converter, a switched-capacitor filter, a class-AB buffer, and an active-RC filter. The lack of on-chip precision capacitors and resistors poses a major challenge in designing these analog building blocks. Another key implementation issue is to maintain the performance of these analog circuits in the presence of substantial substrate noise from the digital signal-processing core. The current consumption is 8.8 mA, and the total active area is 5.1 mm/sup 2/. The channel response meets the Gaussian minimum-shift-keying spectral mask.

A low-power DSP core-based software radio architecture

This paper describes an approach to developing a low-power digital signal processor (DSP) subsystem architecture for advanced software radio platforms. The architecture is intended to support next-generation wide-band spread-spectrum military waveforms. The methodology illustrates how a next-generation programmable DSP core forms the basis for an application-specific integrated circuit (ASIC). It also shows how semiconductor technologies can be integrated into such chips to achieve algorithm performance while minimizing subsystem power consumption. The ASIC is run-time configurable to maintain high flexibility. The range of RF channel modulation (waveforms) and air interfaces is intended to include both wide-band and traditional narrow-band waveforms. Estimated gate counts and power-consumption estimates are presented. DSP circuit-design and power-management strategies necessary to achieve low-power operation are presented. While the architecture discussion focuses on military waveforms, the approach is also applicable to commercial waveforms.

0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.

Embedded software in real-time signal processing systems: design technologies

The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper (Paulin et al., 1997) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support. This situation has resulted in an increased research activity in the area of design tool support for embedded processors. This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.

Arithmetic built-in self-test for DSP cores

A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core.

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-/spl mu/m BICMOS and triple-level-metallization technology, has a 3.9 mm/spl times/4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An application specific DSP for speech applications

A 16-bit digital signal processor core, designed for speech applications in telecommunications and consumer electronics is described. It enables low-cost, low-power DSP processing with several levels of modularity, permitting efficient DSP-based ASIC development. The DSP core can perform speech compression for applications such as digital answering machines and cellular phones.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Programmable DSPs: a brief overview

A brief history of digital signal processors (DSPs), which may become the key to the integration of telecommunications and computation, is presented. A tabular summary of models to date is provided. The recent emergence of DSP cores is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >