Abstract
We are concerned with the design, implementation, and validation of a perception SoC based on an ultrasonic array of sensors. The proposed SoC is dedicated to ultrasonic echography applications. A rapid prototyping platform is used to implement and validate the new architecture of the digital signal processing (DSP) core. The proposed DSP core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering, and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a angle of view span. The design uses a minimum size lookup memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.
Highlights
Ultrasound imaging is an efficient, noninvasive, method for medical diagnosis
Our work dedicated to build an echography device follows this approach. It aims to develop a compact digital signal processing (DSP) core as the main computing engine of an ultrasound imaging system and first prototype it on a programmable logic device (FPGA) subsequent to an SoC device
These signals are amplified with a variable gain (TGC, time-gain-compensation) that depends on the scan depth and, they are digitalized by the analog-to-digital converter (ADC) circuit
Summary
Ultrasound imaging is an efficient, noninvasive, method for medical diagnosis. Employed ultrasound waves allow to obtain information about the structure and nature of tissues and organs of the body [1]. M-mode (M for motion) is 2D display ultrasonic imaging; it displays the depth in tissue according to time of the received echoes. Our work dedicated to build an echography device follows this approach It aims to develop a compact DSP core as the main computing engine of an ultrasound imaging system and first prototype it on a programmable logic device (FPGA) subsequent to an SoC device. This miniaturization enables a design with low power consumption, low noise, and light weight [12].
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