Digital PWM Research Articles

Design of a Self-Oscillating PWM Signal Generator With a Double Integration Loop

A novel digital self-oscillating pulse width modulation (PWM) signal generator with a hysteresis comparator is proposed in this study. The proposed generator, referred to as a “2nd-order PWM signal generator” in this paper, utilizes a double integration loop based upon the concept of delta-sigma modulation for precise conversion. A simple 2nd-order PWM signal generator was initially investigated, but it was found to exhibit impractical behavior: the period of the PWM output signal increased slowly with time. An analysis of the limit cycle state of this simple generator using describing function theory shows that the amplitude of the limit cycle is extremely large. Proportional integral (PI) compensation is therefore used to adjust the limit cycle state by varying the proportional gain and the coefficient of the integral. The use of PI compensation suppresses the amplitude of the limit cycle, thus making the 2nd-order PWM signal generator practical. An analysis of this modified generator reveals that the period of the PWM signal can be controlled by the hysteresis width of the comparator and by the proportional gain. As a test case, a switching frequency of 300 kHz is used for the performance evaluation of the proposed PWM signal generator with a sampling frequency of 12.5 MHz. A noise-shaped output is obtained, and a high-precision, ultra-low-distortion PWM signal with a high effective duty cycle resolution is achieved.

Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique

This paper presents an adaptive all-digital ripple mitigation technique for fully integrated capacitive dc-dc converters. Ripple control is achieved using a two-pronged approach where coarse ripple control is achieved by varying the size of the bucket capacitance, and fine control is achieved by charge/discharge time modulation of the bucket capacitors used to transfer the charge between the input and output, both of which are completely digital techniques. A dual-loop control was used to achieve regulation and ripple control. The primary single-bound hysteretic control loop achieves voltage regulation and the secondary loop is responsible for ripple control. The dual-loop control modulates the charge/discharge pulse width in a hysteretic variable-frequency environment using a simple digital pulse width modulator. The fully integrated converter was implemented in IBM's 130-nm CMOS process. Ripple reduces from 98 to 30 mV, when ripple control secondary loop is enabled for a load of 0.3 V and 4 mA without significantly impacting the converter's core efficiency. Measurement results show constant ripple, independent of output voltage. The converter achieves a maximum efficiency of 70% for Vin= 1.3 V and Vout= 0.5 V and a maximum power density of 24.5 mW/mm2, including the areas for the decoupling capacitor. The maximum power density increases to 68 mW/mm2 if the decoupling capacitor is assumed to be already present as part of the digital design.

Analysis of the Admittance Component for Digitally Controlled Single-Phase Bridgeless PFC Converter

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

FPGA – realization of digital PWM controller using Q-format-based signal processing

This paper first presents a review of very large scale integration signal processing applications using Q-format data representation, through field programmable gate arrays. Also, this paper presents a comprehensive review of Q-format-based applications, which include arithmetic computations in signal processing, linear time-invariant systems, finite impulse response filter, 3-D graphics system, personal digital assistant, and neural networks and power electronic converter control are discussed. Finally, a Q-format-based arithmetic logic unit (QALU) has been designed and developed using very high speed integrated circuit hardware description language. The QALU is used to develop the space vector pulse width modulation control, and the simulation and experimental results are presented.

Study on Magnetic Induced Polarization Technology and Instruments

In order to solve the difficult-ground areas of electromagnetic prospecting, we study magnetic induced polarization technology and instruments. Adopting the techniques such as GPS synchronization, CPLD(Complex Programmable Logic Device), digital PWM(Pulse-Width Modulation) constant current, VHDL(Very high speed integrated circuit Hardware Description Language) programming, a magnetic induced polarization instruments have been developed, which include transmitter, receiver, and three components magnetic field compensator. Instruments have functions such as high-power constant-current supplying, frequency-selective anti-interference receiving, GPS high-precision synchronizing, and amplitude-frequency response of magnetic sensor is flat. Using gradient configuration to obser the original data include magnetic field strength, magnetic polarization rate, phase, and get the magnetometric resistivity, the percent frequency efficiency by the further processing. For magnetic induced polarization instruments, we develop performance testing and the field experiments.

Design and Implementation of Mid-Frequency Magnetron Sputtering Power Supply Based on TL494 and MCU

Abstract. A mid-frequency magnetron sputtering (MFMS) power supply based on TL494 and MCU was introduced. A Buck Chopper and full bridge inverter were applied to the main circuit. The PWM controller TL494 was used in the Buck voltage-regulation control circuit to realize closed loop control. The drive signal of the IGBT in full bridge inverter was based on precise digital pulse width modulator (DPWM) signal produced by the MCU M30290. The DPWM can be set by potentiometer so the power supply can output the square wave with adjustable frequency and duty cycle. The power supply was operated in constant current mode. For micro or strong arcing of the target, different safeguards were adopted by the control circuit. At last, the system test and experimental results show that the stability, reliability and tuning range of the MFMS power supply can meet the requirements of the magnetron sputtering coating.

Plating pulse switching power based on a CPLD

This paper presents a method of using a CPLD to generate a PWM trigger pulse to a full bridge inverter and a chopper circuit. This method results in a very good high power and low voltage large current pulse plating power supply. A single-chip microcomputer is the core of the feedback control system. A fuzzy PID algorithm with SCM and CPLD complexes precisely controls the output voltage, allowing it to maintain a constant value. The system contains a protection circuit that detects output current and output voltage and can correct the system if it enters an over-current abnormal state, ensuring that the driving circuit can effectively drive the IGBT. The circuit is also protected by setting the inverter frequency and dead time of a digital PWM chip. This method for bidirectional pulse plating power supply digital control was verified to be correct and practicable by a Matlab software simulation.

0.7–1.8 GHz multiband digital polar transmitter using watt-class current-mode class-D CMOS power amplifier and digital envelope modulation technique for reduced spurious emissions

A polar transmitter driven by digital input signals for envelope and phase is demonstrated, using a band-switching output resonator to achieve multiband operation. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. The transmitter consists of a current-mode class-D (CMCD) CMOS power amplifier (PA), together with a buck converter with a dead-time generator for improved efficiency. The CMCD PA is tuned by band-switching capacitors that can handle up to 9 V, and is measured to have approximately 30 dBm output power with 31–35% drain efficiency under single-tone testing. The proposed spurious signal reduction technique works to partially suppress quantization noise without increasing power consumption. Overall efficiencies of 27.1/25.6% are obtained at 30.2/28.9 dBm continuous wave (CW) output powers and 0.85/1.75 GHz carrier frequencies, respectively. Spur suppression of 9–10 dB peak is achieved when the proposed algorithm is applied with wideband code division multiple access (WCDMA) modulation.

High Performance FPGA Based Digital Space Vector PWM Three Phase Voltage Source Inverter

This paper focuses on the design of a low power and high performance FPGA based Digital Space Vector Pulse Width Modulation (DSVPWM) controller for three phase voltage source inverter. A new method is proposed to realize easy, accurate and high performance DSVPWM technique based on FPGA with low resource consumption and reduced execution time than conventional methods. Equations of SVPWM are relatively complicated and need a considerable time to execute on a typical microcontroller, therefore a simple method is presented to minimize run time of instructions, e.g. the multiplication operation used in these equations is replaced by a proposed signed and unsigned shifter using 2 to 1 multiplexer unit. Total power consumption of controller is reduced to 37 mW at 100MHz clock frequency. The proposed DSVPWM technique algorithm was synthesized and implemented using Quartus II 9.1V and Cyclone II FPGA, to target device EP2C20F484C6. Also power is analyzed using XPower analyzer. Experimentation and results demonstrate that proposed method have high performance than other works.

Sliding Mode Control Of SMPS

Abstract: Digital control technique is a technique for high frequency switching mode power supply (SMPS). Being widely used in the new generation portable systems, the regulation requirement for high frequency integrated DC-DC switching mode power supply becomes more and more demanding in industry, at very high frequency beyond 10 Mega Hertz range. Analysis and experimental study of buck converter is presented to achieve desired output voltage. The SMPS are emerging in terms of higher dynamic response performances, less output ripple, smaller size and weight. The sliding mode controller is associated with a digital pulse width modulation (DPWM) block to operate at high switching frequency. Sliding mode control (SMC) can reduce the voltage ripple voltage ripple of SMPS. Sliding mode controller will be used by means of analog to digital conversion (ADC) and Digital pulse width modulation (DPWM). Keywords-Analog to Digital converter(ADC), Digital pulse width modulation(DPWM), Sliding mode control

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

AbstractPulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA’s advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.

A New Delay-Line Sharing Based CMOS Digital PWM Circuit

This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 m×370 m. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required.

Fast Charge to Pulse Width Converter for Monolith PET Detector

Currently both preclinical and clinical PET systems are built with pixilated, optically isolated scintillators. The use of optical isolators limits the achievable packing fraction for designs that use small crystals. No optical isolation is necessary in a monolithic scintillation crystal design hence the sensitivity is increased. The light distribution created by a high energy interaction in a monolithic scintillator can be readout by a SiPM-array to determine the 3-D position of the interaction. We have developed a digital pulse width modulation readout circuit that is able to readout many densely packed SiPM-arrays connected to monolithic scintillators. A monolithic scintillation detector requires simultaneous acquisition of the light distribution on multiple sensors unlike in a one-to-one optically isolated pixelated configuration. Therefore, pulse width modulation can reduce the readout complexity of the monolithic scintillation detector. The circuit gives an output signal with a pulse width linear to the incoming charge. Therefore, the circuit provides both timing and intensity information using just one digital line per channel. The charge to pulse-width conversion ratio of the circuit is adjustable (e.g., 33 ns/pC). The trigger jitters σ 41.2 ps between two channels. The PCB offers 8 channels and comes with additional features: The gain variation of a SiPM is compensated over a large temperature range by controlling the bias voltage. We measured from 15°C to 42°C, here it can bring the variation of a SiPM in gain from -21 ns/ °C to +3.8 ns/ °C or stabilizes the variation of the energy resolution between 18 and 20%.

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

SUMMARYThis paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley & Sons, Ltd.

Digital Control of Actual Grid-Connected Converters for Ground Leakage Current Reduction in PV Transformerless Systems

The design of a photovoltaic (PV) grid-connected converter usually comprehends a galvanic isolation between the grid and the photovoltaic panels. Recently, in low power systems, the galvanic isolation has been removed with the aim to increase efficiency and reduce the cost of the converter. Due to the presence of a parasitic capacitance between the photovoltaic cells and the metal frame of the PV panel, usually connected to earth, a high value of common mode current (i.e., ground leakage current) can arise. In order to limit the ground leakage current (which deteriorates the power quality and generates EMI), new converter topologies have been proposed. Their effectiveness is based on the symmetrical (ideal) commutations of the power switches and some of them adopt a further voltage level derived from a capacitive divider of the DC bus voltage. Unfortunately, in actual implementations, asymmetrical power switches transients and variations of this added voltage lead to higher ground leakage current with respect to the ideal case. After a review of the state of the art this paper investigates these two issues and presents a particular solution (based on digital control and PWM strategy) that, in conjunction with a compensation strategy of power switches actual commutations, guarantees low ground leakage current regardless the parameters tolerance of the power circuit. Simulation and experimental results confirm the effectiveness of the proposed solution.

Possible analogy between the optimal digital pulse width modulation technology and the equivalent optimisation problem

A novel nonlinear searching method, immune algorithm (IA), is presented based on the immune theory in biology. This method is applied to resolve the optimal control problem of the sinusoidal pulse width modulation (SPWM) inverter, and the IA is adopted to find the optimal digital SPWM control sequences. Furthermore, the IA well fits with on-line microprocessor implementation. A single-phase full-bridge inverter is considered, and the optimal digital SPWM control sequences are calculated to minimise total harmonic distortion of output waveform. These digital sequences are used in a simulation system and experiment setup to verify the usefulness of the method.

A 3.4 W Digital-In Class-D Audio Amplifier in 0.14 $\mu $m CMOS

In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14 μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface for audio and control that requires only two pins and enables assembly in 9-bump WL-CSP. The complete audio path is discussed that consists of a Parser, Digital PWM controller, 1-bit DA-converters, analog feedback loop and the Class-D power stage. A reconfigurable gate driver is used that reduces quiescent current consumption and radiated emission.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications

A digitally-controlled polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented in a 0.15 μm RF CMOS process. Stacked FETs in a current-mode class-D configuration are used to obtain high breakdown voltage and high efficiency in the output stage, and a doughnut-shaped Guanella reverse balun is applied to achieve a 1-to-4 impedance transformation with less than 1 dB insertion loss. The amplifier has 31 dBm output power with 51% drain efficiency at 0.75 GHz frequency under single tone testing. The output stage is fed by a buck converter employing digital pulsewidth modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5% was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.

Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter

Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter