Digital PWM Research Articles

An Improved High-Resolution DPWM Control Circuit Based on FPGA

Digital pulse width modulation (DPWM) has advantages of strong anti-interference ability, high efficiency and good flexibility, therefore it has been widely used in switching power supply, communications, power control and transform and other fields. This paper proposed a high resolution DPWM control circuit based on field programmable gate array (FPGA), which solved the problem of low resolution and instability of the traditional DPWM control circuit. The principle of the proposed circuit is presented in this paper, and the circuit has been successfully implemented on the Xilinx Artix-7 FPGA development board. The experiment shows that, when the frequency of the circuit is 50 MHz, the resolution of DPWM can reach 78ps, and the proposed DPWM control circuit has wide application prospects.

Architecture of RAM-Accumulator based Multichannel Digital PWM

Traditional counter based digital Pulse Width Modulator (PWM) has been a straightforward architecture. However, realization of multichannel PWM with such design requires considerable logic gates. A novel architecture of multichannel PWM based on the usage of RAM block and frequency word accumulator is proposed. This architecture is capable of producing numerous channels while maintaining its performance. The design was tested in Microsemi SmartFusion A2F200 Customizable System on Chip, giving the result of 7.73% FPGA usage to produce 48 channels of 380Hz 16 bits PWM. The output performance for test application is acceptable.

Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter

A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a counter and a delay line for pulse width conversion. The timing skews along the delay line are detected using a zero-crossing detection scheme and corrected in the digital domain. This calibration can operate continuously in the background. A digital CDA prototype was fabricated using a 65-nm CMOS technology. It includes the aforementioned PWM modulator and DPC. It also integrated an open-loop switching driver to deliver the DPC’s output to a speaker. This digital CDA consumes $875~ {\mu }\text {W}$ under a 1-V supply when the input is zero and no output power is transferred to the external load. It can deliver 13.3 mW to a $32~ {\Omega }$ resistive load in the H-bridge topology with 89% power efficiency. For a 1-kHz sine-wave input, it achieves 95 dBA dynamic range, 93.6 dBA peak SNR, 86.4 dBA peak SNDR, and 0.006% THD at -2-dBFS input level. The core area of the chip is $ {0.87\times 0.5\,\,\text {mm}^{2}}$ .

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

In this paper, the limitations of digital-to-analog (D/A) conversion by Digital Pulse Width Modulation (DPWM) are addressed and the novel Dyadic Digital Pulse Modulation (DDPM) technique for all-digital, low cost, high resolution, Nyquist-rate D/A conversion is proposed. Thanks to the spectral characteristics of the new modulation, in particular, the requirements of the filter needed to extract the baseband component of DPWM signals can be significantly released so that to be suitable to inexpensive integration on silicon in analog interfaces for nanoscale integrated systems. After the new DDPM technique and its properties are introduced on a theoretical basis, the implementation of a D/A converter (DAC) based on the proposed modulation is addressed and its performance in terms of noise and linearity is discussed. A 16-bit DDPM-DAC prototype is finally synthesized on a field-programmable gate array (FPGA) and experimentally characterized.

Control Circuits in Power Electronics: Practical Issues in Design and Implementation [Book News

This book discloses discloses some engineering solutions that usually have no place to be published in papers about control of power electronics converters. Although it is assumed that a skilled engineer can figure out how to implement a published modulator and nonlinear controller, often, the obtained solution is not optimal and takes valuable time. This book presents state-of-the-art techniques to implement modulation schemes, control algorithms, and gate drivers using analog circuits, digital microprocessors, or field-programmable gate arrays (FPGA). The book’s first part covers analog control circuits and converters where analog control circuitry presents higher performance. The second part, “Digital Control Circuits,” includes quantization effects and limit cycles, controller implementation, digital PWM, microcontrollerbased electronic ballasts, and FPGAs with sliding-mode direct control applied to unity power factor boost rectifiers (UPFRs). The third part, “New Trends in Control Circuits for Power Electronics,” starts with intelligent gate drivers, design and control of switched capacitor (charge pumps), and DSP natural frame and sliding-mode control of UPFRs at fixed switching frequency. The last chapters are dedicated to the application of dual-core DSPs in the control of grid-forming converters to microgrids and the usage of computational intelligence (fitness functions, genetic algorithms, and ant colony optimization) to optimize power converters.

Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement

In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50- $\mu \text{A}$ output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 $\mu \text{A}$ to 30 mA in the CCM operation.

Small-signal discrete-time modeling of digitally controlled three-phase PWM boost rectifier under balanced voltage

PurposeThe model for digitally controlled three-phase pulse width modulation (PWM) boost rectifiers is a sampled data model, which is different from the continuous time domain models presented in previous studies. The controller, which is tuned according to the model in continuous time domain and discretized by approximation methods, may exhibit some unpredictable performances and even result in unstable systems under some extreme situations. Consequently, a small-signal discrete-time model of digitally controlled three-phase PWM boost rectifier is required. The purpose of this paper is to provide a simple but accurate small-signal discrete-time model of digital controlled three-phase PWM boost rectifier, which explains the effect of the sampling period, modulator and time delays on system dynamic and improves the control performance.Design/methodology/approachBased on the Laplace domain analysis and the waveforms of up-down-count modulator, the small signal model of digital pulse width modulation (DPWM) in the Laplace domain is presented. With a combination of state-space average and a discrete-time modeling technique, a simplified large signal discrete time model is developed. With rotation transformation and feed-forward decoupling, the large-signal model is decoupled into a single input single output system with rotation transformation. Then, an integrated small signal model in the Laplace domain is constructed that included the time delay and modulation effect. Implementing the modified z-transform, a small-signal discrete-time model is derived from the integrated small signal model.FindingsIn a digital control system, besides the circuit parameters, the location of pole of open-loop transfer function is also related to system sampling time, affecting the system stability, and the time delay determines the location of the zero of open-loop transfer function, affecting the system dynamic. In addition to the circuit parameters discussed in previous literature, the right half plane (RHP) zero is also determined by the sampling period and the time delay. Furthermore, the corner frequency of the RHP zero is mainly determined by the sampling period.Originality/valueThe model developed in this paper, accounting for the effect of the sampling period, modulator and time delays on the system dynamic, give a sufficient insight into the behavior of the digitally controlled three-phase PWM rectifier. It can also explain the effect of sampling period and control delay time on system dynamic, accurately predict the system stability boundary and determine the oscillation frequency of the current loop in critical stable. The experimental results verify that the model is a simple and accurate control-oriented small-signal discrete-time model for the digitally controlled three-phase PWM boost rectifier.

Controlling a mobile manipulator actuated by DC motors and a single phase H-bridge inverter

In this paper, we treat the dynamic feedback control of a mobile manipulator actuated by DC motors using a digital pulse width modulation (DPWM) and a single phase H-bridge inverter in order to achieve a desired trajectory. Firstly, a fuzzy proportional-derivative (PD) controller is proposed to provide the necessary torques for the motion of the robot and to eliminate the effect of external force on the end-effector. Secondly, we aim to determine the current signal needed to drive the DC motors using an H-bridge inverter. Simulation results are given to show the effectiveness of the proposed controller and to demonstrate the coordination of two subsystems in performing the desired trajectory.

Controlling a mobile manipulator actuated by DC motors and a single phase H-bridge inverter

In this paper, we treat the dynamic feedback control of a mobile manipulator actuated by DC motors using a digital pulse width modulation (DPWM) and a single phase H-bridge inverter in order to achieve a desired trajectory. Firstly, a fuzzy proportional-derivative (PD) controller is proposed to provide the necessary torques for the motion of the robot and to eliminate the effect of external force on the end-effector. Secondly, we aim to determine the current signal needed to drive the DC motors using an H-bridge inverter. Simulation results are given to show the effectiveness of the proposed controller and to demonstrate the coordination of two subsystems in performing the desired trajectory.

Explicit Phase Lead Filter Design in Repetitive Control for Voltage Harmonic Mitigation of VSI-Based Islanded Microgrids

Repetitive control strategies have been commonly applied in pulse-width-modulated (PWM) voltage source inverters (VSIs) for many industrial applications. This paper presents a repetitive controller for voltage harmonic mitigation of VSI-based islanded microgrids. The phase delay in the overall control system, e.g., the delay caused by the digital duty cycle calculation, PWM generation, and repetitive controller, has to be compensated by elaborately designed phase lead filters in order to prevent control performance deterioration and system instability. Nevertheless, quantificational analysis and practical design of the time advance unit in such filters are hardly found in existing literature works. In view of this, this paper proposes an explicit analysis of the phase lead filters and a novel design method of the time advance unit in repetitive controllers to ensure system stability. Moreover, with the help of the proposed method, the overall system stability margin is predictable and improved controller performance is achieved as well. The proposed method is implemented experimentally to show the accurate stability margin calculation as well as the excellent steady state and dynamic performances of the repetitive control scheme.

Aliasing-Compensated Polar PWM Transmitter

This brief presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode power amplifiers (PAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance, and increased dynamic range compared to other polar PWM transmitters (PPWMTs) as it does not suffer from AM–AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 and 4 dB in the dynamic range compared to the digital PPWMT and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

Sampled time domain analysis of digital pulse width modulation for feedback controlled converters

Digital pulse width modulation (DPWM) is the main process involved in power conversion of digitally controlled switching power converters. Sampling frequency of analogue to digital (A/D) converter and clock frequency of digital controllers are the two constraints which create time delay in output of the modulator gating pulses. Time delay produces the major effect in terms of low frequency oscillations when the converter operates at high switching frequency. In this study the effect of sampling frequency and clock frequency has been analysed in time domain. The aim of this study is to develop instantaneous mathematical equations for DPWM output, rising edges delay, falling edges delay and develop the analytical method through which the effect of sampling frequency and clock frequency can be minimised. The uniform multisampling technique has been used to develop the mathematical equations for different types of carriers. The clock frequency has been considered for higher frequency operation of the converters. The modulator delay depends upon the sampling frequency, clock frequency, modulation index of modulating to control signal, and the rate of change of the modulating signal. The analytical results are verified through the Xilinx system generator MATLAB/Simulink simulation, and the laboratory experimental results.

Implementation of FPGA based DPWM-Digital PI Closed Loop Controller for Voltage Regulation

Objectives: In this paper, a Field Programmable Gate Array (FPGA) based real time implementation of a closed loop controller for regulating the load voltage under line and load disturbances by generating Digital Pulse Width Modulation (DPWM) is developed. Digital Proportional Integral (DPI) controller is designed to generate the DPWM. Methods: DPWM are developed by two methods: Counter based and Delay line based. The closed loop DPWM activated DC-DC buck converter is simulated using MODELSIM and tested in real time using Xilinx Spartan 3A DSP FPGA. Findings: Hardware results show the regulated load voltage by updating the DPWM control signal duty cycle to compensate the line and load disturbances. FPGA based DPWM provides less complexity in design. Improvements: Hybrid based DPWM method with closed loop control for DC-DC Buck converter could be used for voltage regulation.

Loop‐handover technique for digitally controlled multiple‐output dc–dc converters

The loop-handover (LHO) technique is proposed to overcome the problem of close-loop performance in digitally controlled single-inductor multiple-output dc–dc boost converters during start-up. The presented technique utilises an existing clock source and requires only a small number of blocks. It also occupies a smaller silicon area, thus consuming low power and increasing efficiency. The presented technique is validated with proposed on-chip digital controller with multiple-output boost converter architecture using segmented delay line digital pulse width modulation. Experimental results show a successful close loop with reduced transients by using the simpler LHO technique.

A mixed-signal pulse width modulator for portable SMPS applications

This paper presents a design for a mixed-signal pulse width modulator (MSPWM) integrated circuit that targets the digital control of high-frequency switched-mode DC–DC power supplies (SMPS). Previous designs consider digital pulse width modulators (DPWM) implementations that encounter important design issues, such as power consumption, non-linearity, layout dependency, trimming capability and temperature dependency. This work presents effective solutions, suitable for large-scale production of ICs, since it combines high-precision, high-linearity and temperature-independent standard analog circuits, which are commonly offered by the semiconductor industry, with the simplicity and reuse of digital PID compensation as input. The 8-bit prototype designed for a 0.18-μm CMOS process operates at switching frequency of 2MHz, draws only 96.25μA from a 1.8V supply and takes 0.029mm2, including the non-overlapping control logic of SMPS power devices.

A Multichannel Power-Supply-Modulated Microstimulator With Energy Recycling

This paper presents an energy recycling power-supply-modulated multichannel microstimulator with energy recycling. To improve the stimulation efficiency, the supply of the current driver is modulated according to the instantaneous electrode voltage. Multichannel stimulation together with energy recycling is achieved through decoupling the electrode array from the power supply. A digital pulse-skipping PWM quasi-PID (D-PS-PWM-QPID) controller is proposed to improve the stimulation efficiency.

Reduction in limit cycle oscillation and conducted electromagnetic emissions by switching frequency adjustment in digitally controlled DC-DC converters

Limit Cycle oscillation is a major issue in digitally controlled dc–dc converter due to low resolution digital pulse width modulators (DPWMs). This paper proposes a method for the reduction in limit cycle oscillation by combining the advantages of sigma delta modulation scheme and frequency modulation of switching frequency. In this paper, the correction of quantization error due to low resolution DPWM is accomplished by changing the switching frequency. The error due to the quantization of DPWM was accumulated for few clock cycles and the switching frequency was adjusted in the last cycle such that the duty ratio changes by the number of LSBs corresponding to the quantization error. The quantization error correction increases the effective resolution of DPWM thereby reducing the ripple due to limit cycle oscillations. Further, it also reduces the conducted electromagnetic emissions. Simulations using the SIMULINK model of the converter were carried out to validate the effectiveness of the proposed method. Experimental verification of the scheme was also carried out using a 16 bit DSP Processor which showed around 17 dB reduction in ripple due to limit cycle oscillation and 25 dB reduction in conducted emission levels.

A 500-MHz, 0.76-W/mm Power Density and 76.2% Power Efficiency, Fully Integrated Digital Buck Converter in 65-nm CMOS

In this paper, we propose a 500-MHz on -chip digitally controlled buck converter in which active and passive components are fully integrated on a single CMOS chip. To achieve high-power density, a two-phase interleaving buck converter with negatively coupled inductors is adopted to reduce the silicon area for both inductors and output capacitors. In addition, the proposed on -chip stacked L/C structure can achieve 20% area-saving. Furthermore, to support a 500-Hz switching frequency, we present a low-power digital pulsewidth modulation (PWM) controller that includes a 9-bit time-based analog-to-digital converter and a 15%–90% wide-range digital pulsewidth modulator (DPWM), which occupies only $0.075 \text{ mm}^{2}$ and dissipation of 3 mW. The prototype IC fabricated in 65-nm CMOS can convert a 2.2-V input to a 1.2-V output and achieve a peak power efficiency of 76.2% and maximum power density of $0.76 {\rm W/mm}^{2}$ . Simultaneously, it can deliver 0.84 W and occupy $1.1 \text{ mm}^{2}$ of effective area that includes a pair of 1.54-nH on -chip inductors and 2.63-nF on -chip capacitors.