Digital Logic Gates Research Articles

Novel Practical Built-in Current Sensors

In this paper, we propose three new built-in current sensors (BICS) topologies for on-chip IDDQ tests of analog/mixed-signal (AMS) circuits with the objective to achieve low design complexity, small area overhead and high accuracy. The first two approaches are derived from digital varicap threshold logic (VcTL) gate idea where the structure is modified for analog inputs. The third approach is a switched-cap (SC) methodology with a latch type comparator. Each design and corresponding performance results are provided in details and verified with corner and Monte Carlo analyses. All three approaches are designed as both ATE-assisted and built-in self-test (BIST) solutions. Low drop-out regulators (LDOs) in an AMS system on-chip (SOC) having more than 20 LDOs are selected as circuit under tests (CUT). The target current range is 0–100 μA to cover all LDOs. Moreover, the programmability of these proposed BICS provide a single BICS per chip solution. The overall IDDQ test time is reduced from 927 μs to 280 ns by using proposed BICS (VcTL type with PMOS capacitances). It is a significant improvement in test time and cost considering that the sensor only occupies 0.36 % of a single LDO area or equivalently 0.02 % of entire LDO subsystem.

TCAD Simulation of Digital Logic Gates in Independent Double Gate Transistors – A Comparative Study between Conventional and Junctionless FETs

In this work, conventional independent double gate structure and Junctionless independent double gate structure-based inverters and NAND gates are studied and compared using TCAD simulation. The Junctionless device- based circuits show a larger delay with smaller dynamic power whereas the conventional device-based circuits show smaller delay with larger dynamic power which is a simple power-delay trade-off.

Reconciling fault-tolerant distributed computing and systems-on-chip

Classic distributed computing abstractions do not match well the reality of digital logic gates, which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large Scale Integrated (VLSI) circuits: Massively concurrent, continuous computations undermine the concept of sequential processes executing sequences of atomic zero-time computing steps, and very limited computational resources at gate-level make even simple operations prohibitively costly. In this paper, we introduce a modeling and analysis framework based on continuous computations and zero-bit message channels, and employ this framework for the correctness & performance analysis of a distributed fault-tolerant clocking approach for Systems-on-Chip (SoCs). Starting out from a “classic” distributed Byzantine fault-tolerant tick generation algorithm, we show how to adapt it for direct implementation in clockless digital logic, and rigorously prove its correctness and derive analytic expressions for worst case performance metrics like synchronization precision and clock frequency. Rather than on absolute delay values, both the algorithm’s correctness and the achievable synchronization precision depend solely on the ratio of certain path delays. Since these ratios can be mapped directly to placement & routing constraints, there is typically no need for changing the algorithm when migrating to a faster implementation technology and/or when using a slightly different layout in an SoC.

Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip

Dependability is an important system attribute for microfluidic lab-on-chip. Robust testing methods are therefore needed to ensure correct results. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error prone. We present a built-in self-test (BIST) method for digital microfluidic lab-on-chip. This method utilizes digital microfluidic logic gates to implement the BIST architecture; AND, OR and NOT gates are used to compress multiple test-outcome droplets into a single droplet to facilitate detection with low overhead. These approaches obviate the need for capacitive sensing test-outcome circuits for analysis. We also apply the BIST architecture to a pin-constrained biochip design. A multiplexed bioassay protocol is used to evaluate the effectiveness of the proposed test method.

Ink-jet printed p-type polymer electronics based on liquid-crystalline polymer semiconductors

Poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophenes) (pBTTTs)—currently one of the most promising class of polymer semiconductors—are known to have a low-room-temperature solubility in a broad range of common organic solvents. By judicious selection of a suitable solvent for these rigid-rod-like, liquid-crystalline materials, we ink-jet printed poly(2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene) (pBTTT-C12) into discrete thin-film field-effect transistors (FETs) that display on/off ratios of up to 107 and charge-carrier mobilities in the range of 0.05–0.1 cm2 V−1 s−1. Compared to spin-coated devices, the ink-jet printed devices typically had lower current leakage; indeed, gate-leakage currents were 1 to 2 orders of magnitude lower in ink-jet printed transistors. These overall device performance of ink-jet printed pBTTT-C12 would be sufficient for, for instance, driving simple electrophoretic displays [T. N. Ng, S. Sambandan, R. Lujan, A. C. Arias, C. R. Newman, H. Yan and A. Facchetti, Appl. Phys. Lett., 2009, 94, 233307; G. H. Gelinck, T. C. T. Geuns and D. M. de Leeuw, Appl. Phys. Lett., 2000, 77, 1487–1489; H. E. A. Huitema, G. H. Gelinck, J. van der Putten, K. E. Kuijk, C. M. Hart, E. Cantatore, P. T. Herwig, A. van Breemen and D. M. de Leeuw, Nature, 2001, 414, 599–599; H. E. A. Huitema, G. H. Gelinck, J. van der Putten, K. E. Kuijk, K. M. Hart, E. Cantatore and D. M. de Leeuw, Adv. Mater., 2002, 14, 1201–1204.]. We demonstrate here integration of such ink-jet printed pBTTT-C12 transistors into unipolar digital logic gates, which produced a signal gain of more than 16. This is one of the highest gains reported for a unipolar-based logic gate and demonstrates the potential of pBTTT polymers for high performance application employing simple ink-jet printing procedures conducted in light and ambient air without any special precautions.

Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2/V s, on/off ratios >107, gate leakage current densities <2.8×10−7 A/cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

Extreme temperature 6H‐SiC JFET integrated circuit technology

AbstractExtreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh‐environment applications well above the 300 °C effective limit of silicon‐on‐insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H‐SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

All-optical Digital Logic Gates using Bistable Semiconductor Ring Lasers

This paper demonstrates all-optical digital logic gates using bistable monolithic semiconductor ring lasers (SRLs). With the flexible multi-functional experimental setup, we have experimentally demonstrated the application of SRLs to realize logic functions including: AND, OR, NOR, XOR and all-optical non-retum-to-zero (NRZ) to retum-to-zero (RZ) format conversion. Using bistable semiconductor ring lasers to fulfil all-optical logic functions have the advantages of high output extinction ratio, low switching energy, integration and the potential logic unit in the future.

Automatic System for Measuring and Controlling the Length of a Moving Product in Industries

This paper describes the design and development of a very simple low-cost online system for measuring the length of moving billets in the steel industry. Few photosensors, digital logic gates, and light-emitting diodes are used to track and display the wide variation in billet length. Not a single amplifier or comparator is used in photosensor circuit. The comparative study shows its superiority over other costly dimension-measuring systems, viz., shaft encoder, laser Doppler meter, and charge-coupled-device camera. Before, an operator had a risk of an accident while crossing the hot-cobble-prone area for measuring the billet length. However, today, the length of each billet is displayed in a pulpit, thereby increasing the safety. The measuring error in the billet length, ranging from +100 to -100 mm, is reduced to +50 mm. The fluctuation in linear velocity of an incoming billet to a flying shear causes wide variation in its cut lengths. To overcome this severe problem, the speed of the flying shear is adjusted during the tail end of each billet. The benefit of the system is in the tune of Rs 49.5 times 106 (approximately U.S. $1.26 times 106) per annum, whereas the payback period is less than 15 days. Apart from the different steel products like the slab, bloom, and rail, the developed system is also useful in the dimensional measurement of the products in nonferrous industries.

Micropneumatic Digital Logic Structures for Integrated Microdevice Computation and Control

It is shown that microfabricated polydimethylsiloxane membrane valve structures can be configured to function as transistors in pneumatic digital logic circuits. Using the analogy with metal-oxide-semiconductor field-effect transistor circuits, networks of pneumatically actuated microvalves are designed to produce pneumatic digital logic gates (AND, OR, NOT, NAND, and XOR). These logic gates are combined to form 4- and 8-bit ripple-carry adders as a demonstration of their universal pneumatic computing capabilities. Signal propagation through these pneumatic circuits is characterized, and an amplifier circuit is demonstrated for improved signal transduction. Propagation of pneumatic carry information through the 8-bit adder is complete within 1.1 s, demonstrating the feasibility of integrated temporal control of pneumatic actuation systems. Integrated pneumatic logical systems reduce the number of off-chip controllers required for lab-on-a-chip and microelectromechanical system devices, allowing greater complexity and portability. This technology also enables the development of digital pneumatic computing and logic systems that are immune to electromagnetic interference.

N-nary optical semiconductor photonic transistor

In this paper we present a novel optoelectronic device, called a photonic transistor, and we investigate its properties as they pertain to digital electronic applications. The photonic transistor design is based on a heterojunction configuration similar to a semiconductor optical amplifier, and can be used to construct either N-nary digital logic gates or binary Boolean logic gates. The properties of the photonic transistor are investigated using computer simulations, and the numerical results indicate that such a device can be successfully used in digital optoelectronic applications.

Microfluidic logic gates and timers

We use surface tension-based passive pumping and fluidic resistance to create a number of microfluidic analogs to electronic circuit components. Three classes of components are demonstrated: (1) OR/AND, NOR/NAND, and XNOR digital microfluidic logic gates; (2) programmable, autonomous timers; and (3) slow, perfusive flow rheostats. The components can be implemented with standard pipettes and provide a means of non-electronic and autonomous preprogrammed control with potential utility in cell studies and high throughput screening applications.

Analytical modeling of field-induced interband tunneling-effect transistors and its application

In the room-temperature I-V characteristics of field-induced interband tunneling-effect transistors (FITETs), negative-differential conductance (NDC) characteristics as well as negative-differential transconductance (NDT) characteristics have been observed. The key operation principle of this quantum-tunneling device is the field-induced interband tunneling. To include the effect of interband tunneling, we have developed an analytical equation of interband tunneling current. Due to the inherent SOI-MOSFET structure of the FITET, the current equation of MOSFET has also been included in the analytical equation of the FITET. By comparing the calculated data from these two current components with the measured data, an additional excess tunneling current component has been introduced in the final analytical equation of the FITET. SPICE simulation results with this analytical model have shown good agreements with the experimental results. Also, this analytical model has been applied to verify the functionality of a simple digital logic gate such as XOR and four-level parity checker made by one FITET.

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

Quantum Mechanical Design of Molecular Computers Elements Suitable for Self-Assembling to Quantum Computing Living Systems

There are presented logic gates of molecular electronics digital computers. Maximal length of these molecular electronics digital logic gates are no more than four nanometers and maximal width 2.5 nm. The results of light induced internal molecular motions in azo-dyes molecules have been used for the design of light driven logically controlled (OR, AND) molecular machines composed from organic photoactive electron donor dithieno[3,2-b:2',3'-d]thiophene and ferrocene molecules, electron accepting tetracyano-indane molecule, and moving azo-benzene molecular fragment. Density functional theory (DFT) B3PW91/6-311G model calculations were performed for the geometry optimization of these molecular electronics logical gates. Applied DFT time dependent (DFT-TD/B3PW91) method and our visualization program give absorption spectra of designed molecular gates and show from which fragments electrons are hopping in various excited states. Quantum mechanical investigations of proton Nuclear Magnetic Resonance (NMR) values of Cu, Co, Zn, Mn and Fe biliverdin derivatives and their dimers using ab initio Hartree-Fock (HF) and DFT methods indicate that these modified derivatives should generate from one to twelve Quantum Bits (QuBits). The chemical shifts are obtained as the difference of the values of the tetramethylsilane (Si(CH3)4) molecule Gauge-Independent Atomic Orbital (GIAO) nuclear magnetic shielding tensor on the hydrogen atoms and that of the magnetically active molecules. There are designed several single supermolecule and supramolecular devices containing molecular electronics digital logic gates, photoactive molecular machines and elements of molecular NMR quantum computers that allowed to design several supramolecular Control NOT NMR quantum computing gates. Self-assembling simulations of these molecular quantum computing gates induced idea of self-assembled molecular quantum supercomputer and molecular quantum computing life.

Superconducting nanotransistor based digital logic gates

We describe the fabrication and digital logic operation of superconductingnanotransistors. The nanotransistor is a superconducting weak-link device thathas integrated hot-phonon injector heaters to control its switching critical current.The fabrication process utilizes a self-aligned method, where the heateracts as a mask for reactive ion etching to define the device pattern. Thisdevice is much simpler to fabricate than previously reported controllablesuperconducting transistors and the principle of operation makes it possible to usea single nanotransistor connected to a load resistor as a NOT logic gate,allowing lower power consumption and improved levels of integration.

An analysis of the wire-load model uncertainty problem

Traditional integrated-circuit (IC) design methodologies have used wire-load models during logic synthesis to estimate the expected impact of the metal wiring on the gate delays. These models are based on wire-length statistics from legacy designs to facilitate a top-down IC design flow process. Recently, there has been increased concern regarding the efficacy of wire-load models as deep-submicrometer (DSM) interconnect parasitics begin to dominate the delay of digital IC logic gates. Some technology projections (Sylvester and Keutzer, 1998) have suggested that wire-load models will remain effective to block sizes on the order of 50 000 gates. This suggests that existing top-down synthesis methodologies will not have to be changed substantially since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward and the efficacy of synthesis using wire-load models depends upon technology data as well as specific characteristics of the design and the granularity of available physical information. We analyze these effects and dependencies in detail in this paper and draw some conclusions regarding the future challenges associated with top-down IC design and block synthesis, in particular, in the DSM design era.

Integrated photonic inverter with gain

Photonic integrated circuits (PICs) require inverting gates with gain greater than one to enable logic functionality with fanout and cascade. Optically modulated semiconductor laser technology is speed-limited by the photon cavity lifetime and, therefore, can provide high speed, integrable, digital logic gates. If semiconductor lasers can be configured as photonic inverters with gain exceeding one, then photonic clocks, oscillators, and logic gates would be possible at high data rates. This letter reports the demonstration of a semiconductor laser photonic inverter with an integrated dielectric input waveguide and gain greater than one.

Logic gates using three coupled Josephson junctions

The dynamics of three inductively coupled vertically stacked Josephson junctions have been studied. It is found that the system can be used for realizing ultrafast digital switches and logic gates. Using fluxons as information bits, we pursue the interactive dynamics and identify the possible configurations of structural and dissipative parameters in implementing the elementary logic gates OR, XOR and AND.