Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip

Abstract

Dependability is an important system attribute for microfluidic lab-on-chip. Robust testing methods are therefore needed to ensure correct results. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error prone. We present a built-in self-test (BIST) method for digital microfluidic lab-on-chip. This method utilizes digital microfluidic logic gates to implement the BIST architecture; AND, OR and NOT gates are used to compress multiple test-outcome droplets into a single droplet to facilitate detection with low overhead. These approaches obviate the need for capacitive sensing test-outcome circuits for analysis. We also apply the BIST architecture to a pin-constrained biochip design. A multiplexed bioassay protocol is used to evaluate the effectiveness of the proposed test method.