Digital Integrator Research Articles

An accurate continuous calibration system for high voltage current transformer

A continuous calibration system for high voltage current transformers is presented in this paper. The sensor of this system is based on a kind of electronic instrument current transformer, which is a clamp-shape air core coil. This system uses an optical fiber transmission system for its signal transmission and power supply. Finally the digital integrator and fourth-order convolution window algorithm as error calculation methods are realized by the virtual instrument with a personal computer. It is found that this system can calibrate a high voltage current transformer while energized, which means avoiding a long calibrating period in the power system and the loss of power metering expense. At the same time, it has a wide dynamic range and frequency band, and it can achieve a high accuracy measurement in a complex electromagnetic field environment. The experimental results and the on-site operation results presented in the last part of the paper, prove that it can reach the 0.05 accuracy class and is easy to operate on site.

Design of digital FIR variable fractional order integrator and differentiator

This paper presents an easy and simple method to design variable fractional order digital FIR integrators and differentiators based on fractional order systems. First, closed-form digital IIR fractional order integrators and differentiators have been obtained from the analog rational functions approximations, in a given frequency band, of the fractional order integrator s −m and differentiator s m (0 < m < 1) through the Tustin generating function. Then, closed-form digital FIR fractional order integrators and differentiators by truncation of the digital IIR ones have been derived. Next, polynomial interpolation has been used to design digital FIR variable fractional order integrators and differentiators that can be implemented by the Farrow structure. The main feature of variable fractional order operator is that its order can be changed without re-designing a new fractional order operator. Some examples have been presented through the paper to illustrate the performance and the effectiveness of the proposed design method. The results obtained have been discussed and have been compared to one of the most recent works in the literature using the same design parameters.

Development of a digital integrator for the KSTAR device

The development of an integrator for magnetic diagnostics becomes more important as the pulse length of fusion devices gets longer and longer, especially for present-day superconducting fusion devices. A small offset in the signal can cause a significant drift in the integrator output for long pulse experiments. A lock-in amplifying digital integrator has been developed for Wendelstein 7-X (W7-X). It succeeds in suppressing the drift to a low value but requires about 100 ms for data processing. To shorten the data processing time, a Field Programmable Gate Array (FPGA) built in the digitizer is utilized. Since there is no need to transfer the data to an external computer, the integration can be done in real time. The microprocessor built in the digitizer directly transfers the data integrated in the internal FPGA into the reflective memory installed in the same compact Peripheral Component Interconnect chassis. These features result in a very compact system design. The design and the preliminary results of the digital integrator will be presented.

A 133 MHz Radiation-Hardened Delay-Locked Loop

A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 μ m fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented.

Digital fractional‐order differentiator and integrator models based on first‐order and higher order operators

AbstractIn this paper, new discretized models for fractional‐order differentiator (FOD) (sr) and integrator (FOI) (s−r) using first‐order and higher order operators are proposed. The expansions for FOIs of the first‐order s‐to‐z transform proposed by Hsue et al. are obtained by using the Taylor series and continued fraction expansion techniques. Second‐order Schneider operator and third‐order Al‐Alaoui–Schneider–Kaneshige–Groutage (Al‐Alaoui–SKG) rule have also been fractionalized to obtain expansions of FODs by using the Taylor series. Specifically, in this paper, Hsue operator based on third‐order and fourth‐order models of FOI, Schneider operator as well as Al‐Alaoui–SKG rule based on third‐order, fourth‐order, fifth‐order and sixth‐order models of FOD have been suggested. The stability of the proposed models has been investigated and the unstable ones were stabilized by the pole reflection method. The performance of the proposed models has been compared with that of recent FOD and FOI models based on the Al‐Alaoui operator. Performance results using the proposed discrete‐time formulations are found to converge to the analytical results of FOD and FOI, in the continuous‐time domain. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Using a tracking analog-to-digital converter as the quantizer of a sigma-delta modulator (SDM) has been shown to be an efficient method of reducing the number of comparators. In this paper, a new continuous-time (CT) SDM is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop at a high frequency rate. For a given example, the number of bits of the quantizer is shown to be reduced from five in the original multibit modulator to only one in a quantizer with tracking sampled at three times the original sampling frequency. In addition, the output of the tracking quantizer can be downsampled so that the modulator output has the same resolution and sampling rate as the original modulator. In this way, the design of the digital-to-analog converters in the feedback loop and the decimator filter at the modulator output are not penalized. Furthermore, the digital integrator of the tracking loop can be removed by taking profit of the last CT integrator in the forward path. Finally, the signal component in the forward path can be attenuated by adding a direct path from the modulator input to the last integrator input. As a result, the output swing of the integrators is reduced, improving the linearity of the whole modulator. The new modulators are analyzed and extensive theoretical and simulation results are provided.

Recursive wideband digital integrator and differentiator

In this paper a novel wideband recursive digital integrator and differentiator is presented. The integrator is obtained by interpolating three digital integration techniques and the new differentiator is obtained by modifying its transfer function appropriately. Both the integrator and the differentiator are of third order and highly accurate, thus suitable for real-time applications. Copyright © 2010 John Wiley & Sons, Ltd.

A superconducting transformer system for high current cable testing

This article describes the development of a direct-current (dc) superconducting transformer system for the high current test of superconducting cables. The transformer consists of a core-free 10,464 turn primary solenoid which is enclosed by a 6.5 turn secondary. The transformer is designed to deliver a 50 kA dc secondary current at a dc primary current of about 50 A. The secondary current is measured inductively using two toroidal-wound Rogowski coils. The Rogowski coil signal is digitally integrated, resulting in a voltage signal that is proportional to the secondary current. This voltage signal is used to control the secondary current using a feedback loop which automatically compensates for resistive losses in the splices to the superconducting cable samples that are connected to the secondary. The system has been commissioned up to 28 kA secondary current. The reproducibility in the secondary current measurement is better than 0.05% for the relevant current range up to 25 kA. The drift in the secondary current, which results from drift in the digital integrator, is estimated to be below 0.5 A/min. The system's performance is further demonstrated through a voltage-current measurement on a superconducting cable sample at 11 T background magnetic field. The superconducting transformer system enables fast, high resolution, economic, and safe tests of the critical current of superconducting cable samples.

Design and implementation of a high accuracy sampling wattmeter under non-sinusoidal and off-nominal frequency conditions

Errors may creep in when measuring active power under non-sinusoidal and off-nominal frequency conditions by a conventional regularly spaced sampling digital wattmeter (RSSDW) due to the existence of higher order voltage and current harmonics, and asynchrony between the signal fundamental frequency and the sampling rate. This paper presents design and implementation of a modified regularly spaced sampling digital wattmeter, called M-RSSDW, immune to above mentioned drawbacks of the conventional RSSDW. The proposed method utilizes a modified/ first degree digital integrator design technique, suitable for the distorted power system signals. The harmful truncation errors of asynchronous sampling have been reduced using numerical compensation method. Compared with the well-established technique such as Liangs’ method, the proposed algorithm provides higher degree of immunity and insensitivity to harmonics and frequency deviation. Structural simplicity, wide range of application and reduced computational load are other salient features of the proposed method. Based on simulation studies, the performance and validity of the proposed algorithm at different operating conditions have been presented and its accuracy and response time have been compared with the Liangs’ approach.

Performance Improvement of a DSP-Based Digital Integrator for Magnetic Measurements at CERN

An improved self-calibrating digital instrument for online flux measurements on superconducting magnets for particle accelerators prototyped at the European Organization for Nuclear Research (CERN), in cooperation with the University of Sannio, is presented. The new instrument reduces the online flux analysis time down to 4.00 mus within a resolution of 50 ns. Furthermore, the typical signal-to-noise-and-distortion ratio (SINAD) is significantly improved with respect to the previous version and to the instruments that are currently in use. Details about the design, online measurement principle, and results of the metrological characterization of the new instrument are provided.

Surface-Response-Based Modeling of Digitizers: A Case Study on a Fast Digital Integrator at CERN

A statistical approach to simulation in behavioral modeling for assessing dynamic metrological performance during the concept design of accurate digitizers is proposed. A surface-response approach based on a statistical experimental design allows operating conditions to be systematically and comprehensively explored, simulation to be optimized, and identification and validation uncertainty to be verified. An actual case study on the dynamic metrological characterization of a fast digital integrator for high-performance magnetic measurements at the European Organization for Nuclear Research (CERN) is presented.

Impulse invariance-based method for the computation of fractional integral of order [formula omitted

This paper presents a simple and efficient method for the design of recursive digital fractional order integrator when the order of integration is a real number between 0 and 1. The proposed method is based on the impulse invariance method. First the initial value theorem is used for the selection of the initial value of the impulse response and then any of the well-established signal modeling techniques can be employed for the parameterization of the discrete impulse response by pole-zero models. For a given model order, the approximation accuracy greatly depends on the initial value selected. Illustrative examples are presented to demonstrate the effectiveness and usefulness of the proposed method.

W7-X magnetic diagnostics: Rogowski coil performance for very long pulses

Stellerators can be operated without the need of significant plasma current for generation of poloidal magnetic field components. Wendelstein 7-X (W7-X) is optimized for stiff magnetic configurations by minimizing pressure driven currents, such as bootstrap and Pfirsch-Schluter currents. In Addition to the largely reduced plasma currents, the HELIAS-type device is a low magnetic shear configuration required for magnetic boundary islands. However, the diverting magnetic field structure is already influenced by small net plasma currents. In particular, the W7-AS divertor results revealed a significant sensitivity of the X-point location with respect to favorable edge plasma states. Thus, a precise X-point control for W7-X is envisaged and, although expected net plasma currents range in the order of 10-100 kA only, stabilization by adaptive controllers is foreseen to an accuracy of about 1 kA. This stabilization should be reliable even after 2000 s of plasma operation. A precondition for achieving this is a reliable current detection. For this purpose, W7-X will be equipped with Rogowski of which the first has now been assembled onto one of the plasma vessel sectors. The integral performance and sensitivity inhomogeneities have been tested by employing the digital integrator of W7-X [A. Werner, Rev. Sci. Instrum. 77, 10E307 (2006)] and a cable energized with 200 A, representing the plasma current.

Digital IIR Integrator Design Using Richardson Extrapolation and Fractional Delay

In this paper, a new design of digital integrator is investigated. First, the trapezoidal integration rule and differential equation are applied to derive the transfer function of the digital integrator. The Richardson extrapolation is then used to generate high-accuracy results while using low-order formulas. Next, the conventional Lagrange finite-impulse response fractional delay filter is directly applied to implement the designed integrator. Two implementation structures are studied: direct substitution and polyphase decomposition. Finally, numerical comparisons with conventional digital integrators are made to demonstrate the effectiveness of this new design approach.

38.3: All‐Digital Phase‐Locked Loop with Low‐Temperature Poly‐Silicon Thin Film Transistor for System‐on‐Glass

AbstractThis paper describes an all‐digital phase‐locked loop (ADPLL) for system‐on‐glass (SoG) with low‐temperature poly‐Silicon (LTPS) thin film transistor (TFT). Due to the large variations and mismatches of LTPS TFT, it is very difficult to implement an analog PLL on glass substrate and ADPLL is employed for the timing generation in SoG. The ADPLL is implemented with a 2μm LTPS TFT process technology and consists of 5‐bit delay‐line time‐to‐digital converter (TDC), 7‐bit digitally controlled oscillator (DCO) and digital integrator. with a 20MHz reference clock, the ADPLL is locked within 36 periods of reference clock and shows 930ps peak‐to‐peak jitter.

On-field validation of the new platform for magnetic measurements at CERN

A new platform for magnetic measurements at the European Organization for Nuclear Research (CERN) is presented. The key concepts and the architecture of its main components, a multi-purpose digitizer (fast digital integrator – FDI) and a flexible software framework (flexible framework for magnetic measurements – FFMM), are detailed. The experimental results of the metrological characterization of FDI exhibit a significant advance with respect to the state of the art. Furthermore, the FFMM implementation is shown to provide a reusable and scalable measurement software. Finally, the results of the on-field validation of the platform for field measurements on superconducting magnets in the CERN test facility are discussed.

Digital IIR integrator design using recursive Romberg integration rule and fractional sample delay

In this paper, a digital IIR integrator design based on the recursive Romberg integration rule and the fractional sample delay is investigated. Starting with trapezoidal integrators, the approximation error of the frequency response of digital integrators can be reduced recursively by using the Romberg rule. Although the proposed IIR digital integrators involve the implementation of the fractional sample delay, this problem is easily solved by applying the well-documented design techniques of the FIR Lagrange and IIR allpass fractional delay filters. These techniques lead to the transfer function of the IIR Romberg integrator without using the fractional sample delay. Several design examples are presented in order to demonstrate the effectiveness of the proposed method.

Modeling and Design Rules of a Two-Cell Buck Converter Under a Digital PWM Controller

In this paper, we give a detailed analytical study of a two-cell dc-dc buck converter. We analyse the dynamics of the system by using a discrete time modelling approach and considering a digital controller. This controller includes a dynamic compensator in the form of a digital integrator for the output variable regulation. The discrete time model for the whole system is used to predict the instability of the system when some design parameters are varied. To facilitate the design, an approximated closed form discrete time model is derived in the form of a recurrence equation which accurately describes the dynamical behavior of the system. The Jury test is applied to the characteristic polynomial in order to obtain stability boundaries in the design parameter space. Some design rules to obtain optimal transient behavior are also given. Numerical simulations and experimental measurements confirm the theoretical predictions.

Performance simulation of a digital integrator for magnetic measurements at CERN

A fast digital integrator (FDI) has been designed at the European organization for nuclear research (CERN) for improving performance of state-of-art instruments for testing superconductive magnets in particle accelerators. In this paper, at first, the FDI architecture and the related main uncertainty sources are highlighted. Then, the numerical analysis of the instrument metrological performance is shown, by focusing both on deterministic errors and uncertainty effects, with the aim of addressing main design challenges.

Digital Integrator for Fast Accurate Measurement of Magnetic Flux by Rotating Coils

A fast digital integrator (FDI) with dynamic accuracy and a trigger frequency higher than those of a portable digital integrator (PDI), which is a state-of-the-art instrument for magnetic measurements based on rotating coils, was developed for analyzing superconducting magnets in particle accelerators. Results of static and dynamic metrological characterization show how the FDI prototype is already capable of overcoming the dynamic performance of PDI as well as covering operating regions that used to be inaccessible