Digital IC Research Articles

Calibration of drift-diffusion model in quasi-ballistic transport region for FinFETs

In the past few years, conventional digital IC technologies have developed rapidly and the device structures have shrunk down to the quasi-ballistic region which strongly affects the device characteristics. The usage of the steady-state transport model and the parameters of the drift-diffusion (DD) method may not correctly model the performance of these devices, including the velocity distributions of the carriers. Several previous studies have suggested modifying the transport parameters of the DD model to continue using it in the quasi-ballistic region. In this paper, a Monte Carlo (MC) simulator is used to calibrate the transport parameters of the DD model for silicon FinFETs. The device features obtained via the parameter-calibrated DD model fit well with the MC simulator. The trends of the calibration factors are also investigated for varying drain voltage, gate voltage, fin width and gate length.

Convolutional neural network for bio-medical image segmentation with hardware acceleration

Application of artificial intelligence in Bio-Medical image processing is gaining more and more importance in the field of Medical Science. The bio medical images, has to go through several steps before the diagnosis of the disease. Firstly, the images has to be acquired and preprocessing has to be done and the data has to be stored in memory. It requires huge amount of memory and processing time. Among the preprocessing steps, edge detection is one of the major step. Edge detection filters the unwanted details in the image, and preserves the edges of the image, which describe the boundary of the image. In biomedical application, for the detection of the diseases, it is very essential to have the boundary detail of the acquired image of the organ under observation. Thus it is very essential to extract the edges of the images. Power is one of the main parameters that have to be considered while dealing with biomedical instruments. The biomedical signal processing instruments should be capable of operating at low power and also at high speed. In order to segregate the images into different levels or stage, we use convolutional neural networks for classification. By having a hardware architecture for image edge detection, the computational time for pre-processing of the image can be reduced, and the hardware can be a part of acquisition device itself. In this paper a low-power architecture for edge detection to detect the biomedical images are presented. The edge detection output are given to the system, which will diagnose the diseases using image classification using convolutional neural network. In this paper, Sobel and Prewitt, algorithms are used for edge detection using 180 nm technology. The edge detection algorithms are implemented using VLSI, and digital IC design of the architecture is presented. The algorithms for edge detection is co-simulated using MATLAB and Modelsim. The architecture is first simulated using CMOS logic and new method using domino logic is presented for low power consumption.

Design of Digital CMOS Neuromorphic IC with Current-starved SRAM Synapse for Unsupervised Stochastic Learning

This paper proposes a current-starved SRAM circuit for use as a synapse to support a biological learning of spike-timing dependent plasticity. If the driving strength of SRAM is limited both when writing a new state and restoring the previous state, then programming the opposite synaptic weight requires several densely-repeated write operations. The synapse takes only stochastically-meaningful stimuli for training, and rejects random and noisy inputs; as a result it achieves successful learning even with binary SRAM. The proposed synapse is applied to a three-layer neuromorphic network of spiking neurons that includes a receptive synaptic array and a projective synaptic array. The network is designed with a 28-nm digital CMOS process. Applying an unsupervised learning to only the projective synapses with the receptive synapses fixed at randomly given, the network successfully memorizes multiple overlapped image patterns and recalls the trained patterns if the images are distorted.

VCSEL-Based In-Circuit Status-Monitoring and Effects-Diagnosis Method for HPEM Susceptibility Test on Digital Electronic Equipment

This paper proposes the method of using bias-free vertical-cavity surface-emitting lasers (VCSELs) for in-circuit monitoring and effects-diagnosis of digital electronic equipment undertaking HPEM susceptibility test. A circuit level model for typical single mode VCSEL and standard I/O buffer information specification model for I/O ports of digital ICs are built to simulate VCSEL's load effects to the digital IC from specific logic families, as well as VCSEL's light output. Simulation results show that VCSELs connected in parallel to IC's I/O ports can be lighted up and its light output can achieve remote status-monitoring of I/O ports’ states in real time, while its load effects to the I/O ports are light enough not to deteriorate its signal integrity or disturb the circuit's normal operation. An experiment is performed on commercial mini sized drone to validate this study and demonstrate this method's feasibility and advantages in equipment level HPEM susceptibility test.

Energy-efficient digital and wireless IC design for wireless smart sensing

Wireless smart sensing is now widely used in various applications such as health monitoring and structural monitoring. In conventional wireless sensor nodes, significant power is consumed in wirelessly transmitting the raw data. Smart sensing adds local intelligence to the sensor node and reduces the amount of wireless data transmission via on-node digital signal processing. While the total power consumption is reduced compared to conventional wireless sensing, the power consumption of the digital processing becomes as dominant as wireless data transmission. This paper reviews the state-of-the-art energy-efficient digital and wireless IC design techniques for reducing the power consumption of the wireless smart sensor node to prolong battery life and enable self-powered applications.

Optical interaction in active analog circuit elements

This publication introduces (spectral) photon emission (PEM) and electro-optical frequency mapping (EOFM/LVI) measurements to analog circuit elements (simple, cascode and low-voltage current mirrors). Different operating conditions of the devices are probed and the voltage dependence of the signals is analyzed. Results partly show close similarities to optical probing of digital IC's, but also differences in voltage dependence and signal levels due to more complicated voltage and signal distributions along the devices.

Qualification extension of automotive smart power and digital ICs to harsh aerospace mission profiles: Gaps and opportunities

Historically the aerospace market has always chosen high level reliability solutions through customized technologies and processes, in order to cope with the requirement driven by mission profiles and application environment severity.In parallel, Automotive market required more and more high reliability targets. As a consequence, the qualification activity has evolved, passing from a stress driven approach strictly based on AEC-Q100 standard to a failure mode driven approach oriented to satisfy the robustness criteria required by TIER1 and Car Makers.Starting from this scenario, new market opportunities for Automotive devices can be identified, since the most reliable of them are today eligible to be sold to aerospace manufacturers with important cost saving thanks to massive production volumes of consolidated technologies.A gap may still persist and has to be carefully explored. First of all, a study of the different application constraints has to be carried out and the potential failure modes activated by Aerospace cold unbalanced mission profile, atmospheric pressure and radiations have to be analysed.Experimental evidences have been collected as first step on advanced CMOS technologies, and their extension to the smart-power families, where digital and power coexist together, will be shortly discussed in this paper.

Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating

Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been recently proposed to reduce leakage current during the standby mode in large-scale Digital ICs in nano regime area. However, detailed analysis of the conditions at which the NEMS devices will have impact is missing. In this brief, the technique of power gating is analyzed with a NEMS switch using detailed circuit level simulations to obtain the conditions under which one can obtain net energy savings as compared with FinFET-based power gating. Finally, applicability in the energy reduction on a futuristic system-on-chip for mobile platform made using 14 nm gate length FinFET device is evaluated.

A Simple Control Strategy Using Speedy Transient Response for Multiphase Buck Converter

The high performance of recent originating digital processors requires power supply for transient output, firm voltage regulation and high current. Industry has taken up interleaved multiphase synchronous buck converters for meeting such demands. Application of the voltage mode (ripple) hysteretic strategy to multiphase Voltage Regulator Units (VRU) would help satisfying many of the upcoming digital processors and IC’s powering demands. This arises from the use of the various advantages that can be obtained from this technique. This current division method is known for several benefits it provides: easy accessibility in application to all control methods, with freedom from the prime control technique in voltage regulation loop, absence of any necessity for current reference, better accuracy in current division of equal magnitude at almost every load conditions in standstill and transients. As against this, there are several challenges that involve distribution of multiple control signals, current sharing and sensitivity to noise, high speed comparators, hysteretic band accuracy and stable at large load transients. In addition, application of the current division technique presented was made to a multiphase voltage mode ripple controlled Buck Converter that produced a novel and easy control strategy having minimum output voltage ripples and speedy transient output.

Role of Microprocessors, Digital ICS in Electric Drive Control and Significance of FPGA –Review

Role of Microprocessors, Digital ICS in Electric Drive Control and Significance of FPGA –Review

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits

Side channel attacks have become a major threat to hardware systems. Most modern digital IC designs utilize sequential elements which dominate the information leakage. This paper reports the first unified analysis and comprehensive comparison of known secure flip-flop circuits. We present a device level analysis of the information leakage from these FFs and propose several evaluation metrics to quantify their security. We show that simulated PA attacks that utilize the information evaluated by these metrics at the gate-level extract more information at the module-level.

Robust Study and Design of a Low Power CMOS CSVCO using 45nm Technology

This paper consist of the design and detailed study of a three stage Current Starved Voltage Controlled Oscillator having a very low voltage supply of 1V with low phase noise. The Three stage CSVCO is designed. This work is being done on Cadence virtuoso analog and digital IC design tools with gpdk 45nm CMOS technology process. The voltage supply is taken to be 1V which is low and quite useful according to the latest trends. The center frequency is taken to be 2.4 GHz which is best suitable for satellite and many other applications. The proposed CSVCO consumes low power, low area, low phase noise and high oscillation frequency. The design procedure adopted and the simulation results acquired are illustrated. This CSVCO is suitable for a fast locking PLL, for frequency synthesizer, for clock generation and recovery etc. The results obtained are compared with the previous works and improvements are observed. The Phase noise of the proposed CSVCO is less as compared to the other works.

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

Study of DC Characteristics in Reliable 4-T Relay Technology for Ultrafast Low Energy NEM Digital IC’s

Fig 1. (a) Schematic illustrations of the four terminal-relay structure. (a) Isometric view and plan-view SEM image. (b) Cross-sectional view along the channel (A-A’) in the OFF state. (c) Cross-sectional view along the channel (AA’)

Design Flow of a Digital IC: The role of digital IC\/SOC design in CE products

The Central Module of Consumer Electronics (CE) products is a miniature-sized IC that finds wide-spectrum applicability from kitchen appliances to automobiles, aircraft, or any embedded systems. The system in these modern CE products is built as an analog/mixed-signal SOC (AMS-SOC). In a typical case, the digital circuits are the main computational modules, whereas the analog or mixed-signal components are interfacing circuits. Proficient design of digital ICs has become more important because it is one of the significant driving factors of efficient system design in this current mobile electronics era. The various factors involved during IC design, such as speed, power, and reliability, are shown in Figure 1.

On Efficient Minimization Techniques of Logical Constituents and Sequential Data Transmission for Digital IC

Objectives: In this paper, a systematic analysis is done on existing logical architecture of on-chip data transmission for a digital integrated circuit like System-on-a-Chip (SoC), Network on Chip (NoC), etc. for fast data communications. Analysis: For systematic comparisons, buses are categorized in different topology based on logical architectures and in the different protocol depending on their communication mechanism. The paper illustrates the operation of the arbiter mechanism. The paper present a systematic analysis of the topology and protocols based on sequential data transmission methods, the priority of accession mode, flexibility and compatibility and performance analysis for the cases of different logic structures and clock frequencies. Finding: Multiple buses are suitable to connect maximum number blocks to avoid the overloading effect on a single bus. The Matrix bus seems to be the best solution for attaining high-speed block data communication, but not energy efficient where as share bus is the most energy efficient bus but not suitable for high-speed operation. Several existing On-Chip Communication Architecture (OCBCA) in the literature and compare them according to their structure, advantages, limitations and application criteria to achieve full performance by minimized logical constituent and the different functional blocks using different communication channels and interconnections. Novelty: Comparison among the all existing on-chip interconnection topology, protocols and minimization techniques of logical constituents.

Modeling and analysis of vertical noise coupling in TSV-based 3D mixed-signal integration

This paper reports on modeling and analysis of vertical noise coupling between adjacent chips in TSVs-based 3D mixed-signal integration. The coupling between clock channel in digital IC and channel routing wires (CRWs) in analog IC is studied in both frequency domain and time domain. According to physical architecture, a broadband equivalent circuit model of vertical noise coupling is proposed. The comparison of S parameters from full-wave electromagnetic (EM) simulation and a circuit model shows a good agreement. The coupling mechanism is discussed from transfer impedance between clock channel and CRWs. The impacts of design variables (such as geometry dimension, 3D stacking process, layout floorplan) on noise coupling are investigated. Four approaches are proposed to reduce the vertical noise coupling and compared with the baseline model. Finally, the time domain analysis shows that the rising/falling time determines peak-to-peak noise voltage and the far-end exhibits larger noise than the near-end.

Novel electromagnetic bandgap structure to mitigate simultaneous switching noise for mixed-signal system applications

This paper proposes a novel T-shape electromagnetic bandgap (EBG) structure to suppress simultaneous switching noise (SSN) in mixed-signal systems. Noise is generated due to simultaneous switching multiple drivers in the digital ICs. It is called as SSN. It could propagate between power and ground planes of underlying PCB platform and interfere with the functionality of nearby RF/Analog ICs. So, the RF modules are isolated from the digital module for proper functioning of entire mixed-signal system. A high-impedance surface, called T-shape EBG has been implemented between digital and RF modules. It will exhibit the characteristics of bandgap for a wide frequency range to suppress the propagation of switching noise. A single unit-cell of T-EBG is periodically patterned over one side of the PCB and the other side is kept continuous. In this paper different characteristics of T-EBG have been simulated and verified with the measurement results. A 3 × 3 T-EBG layout provides an isolation of −40 dB from 0.72 to 6.39 GHz. A scaled version of T-EBG is used to shift the bandgap towards higher frequency range from 2.22 to 7.19 GHz. Also, a novel layout methodology has been proposed to broaden the bandgap from 2.02 to 18.84 GHz without reducing the thickness of dielectric substrate.

All-Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

Digitally implementable LDOs embedded within digital functional units augment their analog counterparts for ultrafine-grained power management in digital ICs. Digital load circuits represent load currents with large and infrequent current transients and require a wide voltage range of operation, preferably down to the threshold voltage ( $V_{{\rm TH}}$ ) of the transistor. This paper presents a discrete-time, fully digital, scan-programmable LDO macro in a low-power 0.13-μm technology operating down to 1.07×, the transistor $V_{{\rm TH}}$ , and featuring greater than 90% current efficiency across a 50× current range through fine-grained clock gating and adaptive control. An 8× improvement in transient response time to large load steps is achieved through switched mode control. Both transient and steady-state operation models and measurements of the LDO are presented.

Verilog Design of Programmable JTAG Controller for Digital VLSI IC’s

The objective of this work is to design and implement a custom reconfigurable JTAG controller in Verilog. It can be directly inserted in to a new digital IC designs with little modifications. It is fully compatible with IEEE 1149.1 standards. Additional programmable private instructions can also be added in to the design. A secure access mechanism is provided in to the controller which helps in protecting the system by preventing the un-authorized users from interfering with the system functions. A locking and opening mechanism and a password key based access control were incorporated as part of the JTAG controller module. The controller was configured to fit into different ISCAS’89 digital VLSI benchmark designs and results are analysed. It is observed that as the design size increases the area and power overhead decreases but the number of boundary scan vectors increases. All the designs were written in Verilog and RTL simulations were performed using Cadence NC-Sim Simulator. Cadence Encounter Test Architect 13.1 was used to check the boundary scan flow and analysis. A line graph to depict the power and area overhead is also shown. Complete performance analysis of the ISCAS’89 designs with and without the JTAG controller was performed. The power and area overhead was found to be negligible as the size of the VLSI designs increases.