Digital Frequency Synthesizer Research Articles

Performance Realization of CORDIC based GMSK System with FPGA Prototyping

The Gaussian Minimum Shift Keying (GMSK) modulation is a digital modulation scheme using frequency shift keying with no phase discontinuities, and it provides higher spectral efficiency in radio communication systems. In this article, the cost-effective hardware architecture of the GMSK system is designed using pipelined CORDIC and optimized CORDIC models. The GMSK systems mainly consist of the NRZ encoder, Integrator, Gaussian filter followed by FM Modulator using CORDIC models and Digital Frequency Synthesizer (DFS) for IQ Modulation in transmitter section along with channel, the receiver section has FM demodulator, followed by Differentiator and NRZ decoder. TheCORDIC algorithms play a crucial role in GMSK systems for IQ generation and improve the system performance on a single chip. Both the pipelined CORDIC and optimized CORDIC models are designed for 6-stages. The optimized CORDIC model is designed using quadrature mapping method along with pipeline structure. The GMSK systems are implemented on Artix-7 FPGA with FPGA prototyping. The Performance analysis is represented in terms of hardware constraints like area, time and power. These results show that the optimized CORDIC based GMSK system is a better option than the pipelined CORDIC based GMSK systems for real-time scenarios.

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured.

The research of the spectral characteristics of the voltage inverter exciter bandwidth

The analysis of the structural scheme of the reflectometric system exciter was carried out. We show that the basic block diagram for the construction of range of the inverter is a single ring exciter digital frequency synthesizer. The mathematical model of range of the inverter exciter provides an analysis of the structural schemes of inverter with pathogen spectral methods. These expressions of the spectral power density of the phase fluctuations allowed to take into account the effect of the circuit elements of the inverter of the pathogen on its spectral characteristics and calculate the dispersion, the average deviation of the phase in the frequency band and the mean square raid exciter output signal phase.

Research and Design of DDS Low Frequency Signal Generator Based on FPGA

Signal generator is the most widely used basic instrument in the field of electronic technology. The research and development of DDS low frequency signal generator based on FPGA has certain practical significance. With the core of EP2C8Q208C8N and the necessary peripheral analog circuit, a low frequency signal generator based on direct digital frequency synthesis technology is designed and its output performance is tested under the control of Verilog program.

Long Range Backscatter Communication Method Based on Direct Digital Frequency Synthesis

Long Range(LoRa) Backscattering Communication (BC) not only has the advantages of low cost and low power consumption, but also has a long communication distance. However, the existing LoRa BC scheme is complex and can not be applied to actual engineering. For this purpose, a new LoRa BC method is proposed. A Direct Digital frequency Synthesis (DDS) technique is used to generate a square wave with a linear frequency variation as a LoRa scattering modulation signal. For the first time, the prototype of LoRa BC system based on MCU is demonstrated. Experimental results show that design can successfully realize backscatter communication at any position between the station and the receiver which are 208 meters apart, while being compatible with commodity LoRa chipset. In addition, the method is also applicable to an Application Specific Integrated Circuit (ASIC) design, which enables the LoRa backscattering IC to have higher robustness, lower cost, and lower power consumption.

74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations

In this brief, a four-stage pipeline read only memory (ROM)-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed. To attain higher spurious-free dynamic range (SFDR) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The second-order parabolic equations with proper coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation using the TSMC 0.18- $\rm {\mu }\text{m}$ CMOS technology cell library and on-silicon measurements, where the maximum SFDR is 74 dBc, 0.018-mW/MHz power dissipation, and the maximal clock frequency is 71.9 MHz.

Влияние акустического замораживания на показатели структуры сублимированной клубники

Исследование посвящено вопросам изменения структуры клубники, предварительно замороженной традиционным способом в условиях естественной конвекции или замороженной с наложением микровибрации. Микровибрацию создавали в воздушной среде морозильной камеры в лабораторном устройстве ABAT-20/1-AEF, оснащенным цифровым синтезатором частот оригинальной конструкции, с генерации электромагнитных полей мощностью от 1 до 500 Вт/м3 с пакетами одно и двух полярных прямоугольных импульсов в диапазонах частот 10 мГц – 5000 кГц. Замороженные в двух вариантах ягоды подвергали вакуумной сублимационной сушке на оригинальном лабораторном стенде СВП-0,36. Температура сублимации составляла минус 30 + 1°C, на этапе досушки температура была равной 38-40 °C. Общая длительность цикла высушивания составила 14-16 часов в зависимости от размера ягод. Ягоды сушили до конечной влажности 1,7%. В высушенных образцах изучали микроструктуру и оценивали показатели пенетрации, предельного напряжения сдвига, водопоглощения, определяли сорбционные свойства и органолептические показатели. Отмечено, что наложение микровибрации позволяет формировать мелкокристаллическую структуру льда и обеспечивать сохранность тканевых структур в высушенных продуктах. Исследования микроструктуры показали, что уровень сохранности клеточных структур при наложении микровибрации составляет 60-70%, в сопоставлении с 25-30% при традиционном замораживании. Выявлено, что применение микровибрации в процессах замораживания позволяет улучшить структурно-механические характеристики высушенных ягод клубники и их сохранность в процессе фасовки и транспортировки. Органолептические показатели у исследуемых образцов при двух вариантах замораживания остаются практически одинаковыми. В результате проведенных исследований отмечено, что наибольший эффект от наложения микровибраций отмечен для ягод меньшего размера.

DIRECT DIGITAL FREQUENCY SYNTHESIZER IN THE RESIDUE NUMBER SYSTEM

The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

Microwave Synthesis for the PTB Cesium Fountain Clocks

Microwave synthesizers that are used to generate microwave signals for the CSF1 and CSF2 fountain clocks at the Physikalisch-Technische Bundesanstalt (PTB) are described. The synthesizers are based on a divider chain and a digital frequency synthesis and have been designed for use with an optically stabilized microwave oscillator. They have been designed in a modular fashion to assure long-term operation and low down times. The results of an in-depth examination of spectral purity, phase noise, and long-term phase stability are presented. Also, the implications of measured parameters on the fountain timing are assessed. Two methods of suppressing the frequency-shifting effect of microwave leakage fields are implemented, with one method in each synthesizer. The first method uses an interferometric switch, and the second uses a phase-coherent and phase-preserving frequency detuning scheme; their contribution to the systematic uncertainty of the fountains is assessed. The overall systematic uncertainty contribution associated with the fountain electronics is below $1 \times 10^{-17}$ for both fountain clocks.

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

In ac motor drives, the fixed-frequency harmonic components of output voltage and current from the inverter with fixed-frequency pulsewidth modulation usually lead to electromagnetic interference (EMI). The spread spectrum clock generation (SSCG) is a widely used solution for this problem. Adjusting the switching frequency to reduce EMI is one kind of practicable scheme among SSCG methods. How to design an optimal or suitable modulation profile is a research emphasis of scholars and has been discussed in depth in many literatures. However, apart from the modulation profile, the mode and quality of carrier are also important and can be improved. In most frequency modulation methods, due to the limitation of the conventional carrier generation mode, the implementation of the new frequency instruction has to wait for the termination of the last switching period. In order to eliminate the waiting state and design a simpler algorithm, this paper has proposed a wait-free phase-continuous carrier frequency modulation (WPCFM) strategy by combining the direct digital frequency synthesizer theory and proper temporal planning of control interruptions. Besides, a theoretical analysis of WPCFM, including quantization error, frequency jitter, phase delay, and voltage distortion, has been finished. Moreover, compared with conventional methods, a more convenient, feasible, and simpler field-programmable gate array based algorithm implementation method and the control structure of WPCFM are also introduced. The analysis shows that, although WPCFM causes a slight increase of the current ripple, it can solve the partial frequency nonuniform distribution problem of the conventional method, and it has a potential value of applications in the wide band gap motor drive systems. The effectiveness of the WPCFM is verified by several sets of EMI reduction experiments where classical periodic carrier frequency modulations are applied.

Measurements of Periodic Signals Phase Shifts with Application of Direct Digital Synthesis

The development of new methods and high-bit instruments for measuring phase shifts of high-frequency periodic signals with high speed for radar and radionavigation tasks is an actual task. The purpose of this work is to create a new phase shift meter for high-frequency periodic signals based on the double-matching method using direct digital frequency synthesis.On the basis of the proposed mathematical model of phase shift measurements of periodic signals by the method of double coincidence using the statistical accumulation of pulse coincidences, a functional diagram of a digital phase shift meter of periodic signals using a direct digital frequency synthesizer is developed. This allowed the implementation of an 8-bit converter phase shift signal to the code on the programmed logic integrated circuit EPM240T100C5N firm Altera.The digital phase shift meter of periodic signals based on the double-matching method consists of two comparators, two short-wave pulse generators, a direct digital frequency synthesizer, two pulse counter control circuits, two short pulse coincidence circuits, two pulse counting circuits, four clock counters, four registers, a microcontroller and an indicator. Block diagram of a double-matching digital phase meter using direct digital sintesizer use minimal hardware logic.In the developed phase shift meter, due to the use of the double-matching method, the time delay between signals does not depend on the period of input signals and can be found when changing the frequency of periodic pulses in wide limits. Measurement errors will be determined mainly by the duration of the pulses of coincidence. The use of statistical accumulation of pulse coincidence in the basis of the work allowed eliminating the restrictions on the duration of pulses of known non-ionic meters.On the basis of the obtained results, a high-bit converter of phase shifts of high-frequency periodic signals into a binary code with high speed for problems of industrial tomography, radar and radionavigation can be developed.

Power-effective ROM-less DDFS Design Approach with High SFDR Performance

A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)- rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS.

High-precision synchronization detection method for bistatic radar.

To improve the accuracy of radar ranging and positioning under complex backgrounds, a high-precision synchronization detection method for bistatic radar is proposed based on different-frequency phase processing. First, the transmit signal and receive signal are converted to radio frequency pulses by frequency conversion. Then, the transmit signal is roughly measured with a field-programmable gate array. The obtained rough signal is used as the reference signal under the control of the direct digital synthesizer frequency synthesizer. Second, the transmit signal and receive signal are each synchronized with the reference signal in a different-frequency phase detection. These detection results are used as the starting signal and stopping signal of the counter gate. Finally, all the signals are counted, and the time synchronization between the transmit signal and the receive signal is implemented by processing the counting value. The experimental results show that a time synchronization precision of 1.5 ps and a frequency stability of 6.2 × 10-13/s can be reached. This method has the advantages of a fast time response, good noise suppression, and high measurement precision and strong system reliability.

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

In this paper, we propose a 60-GHz fractional- ${N}$ digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( $1/\!f^{3}$ ) and thermal ( $1/\!f^{2}$ ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with $\Sigma \Delta $ dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to $1/\!f^{3}$ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.

Design of Charge Signal Generator Based on DDS Technology

The charge signal generator was designed by using Field Programmable Logic Gate Array(FPGA), Digital to Analog Conversion (DAC) circuit and charge conversion circuit. The Direct Digital Frequency Synthesis (DDS) was used to realize the frequency modulation, amplitude modulation and phase modulation of the signal. At the same time, the operating principle of the DDS technology and the design ideas of the analog circuit were described in detail. Under the Modelsim software platform, the function simulation of the program was carried out, and the real-time signal was captured and displayed by the SignalTap II logic analyzer. The correctness of the program was proved by the simulation results and the actual waveform. The voltage signal was converted into the charge signal, and joint debugging with the charge converter and the conditioning amplifier. Tests showed that the output waveform can meet the design specification and this proves the validity and reliability of the charge signal generator. The charge signal generator can be used as a standard signal source for the installation and commissioning of loose parts and vibration monitoring system, and it can be used for overhaul inspection of nuclear power stations.

The design of a wide bandwidth time marker generator.

The Time Marker Generator (TMG) is an important instrument that is used to calibrate the time base of an oscilloscope. If a direct digital frequency synthesizer is used to generate the necessary waveforms, there is serious distortion in the generated square wave when the ratio of the sampling frequency to the output frequency is non-integer. In addition, the look-up table (LUT) in the direct digital waveform synthesizer needs a large storage capacity to generate a narrow triangular wave at a low output frequency. This paper proposes a design that will generate the time marker whose samples are synthesized by real-time calculation instead of storing them in a LUT. We also propose an M waveform data synthesizer with a parallel structure (M-WDSPS) to reduce the operating clock frequency of the field programmable gate array (FPGA). We built a 4-WDSPS TMG based on this design and reduced the required clock frequency from 1 GHz to 250 MHz, thus making the implementation possible in an FPGA. Our proposed TMG design can provide square wave, pulse wave, narrow triangular wave, and linear triangular wave with different amplitudes in two operating modes: normal mode and highlight mode. The TMG we constructed can provide the time marker with an output frequency range from 10 mHz to 111 MHz, a rising/falling edge time lower than 1 ns, regardless of whether the output frequency is low or high, and a frequency stability lower than 0.1 ppm.

Broadband Frequency Synthesizer for Acoustooptics

A broadband digital frequency synthesizer for acoustooptical filters has been designed and studied. The range of synthesized frequencies has been expanded as compared to synthesizers based on phase locking. The interface for control of the proposed design has been developed. Using the user can enter frequency values by himself. A prototype of a dual-channel frequency synthesizer with possibility of independent operation of channels has been produced.

Comparison between Trigonometric, and traditional DDS, in 90 nm technology

The Direct Digital frequency Synthesizer (DDS) is an architecture largely used for the generation of numeric sine and/or cosine waveforms in different applications. In this work, authors compare two different DDS architectures: the traditional architecture, based on the exploitation of quarter wave symmetry, and the Symon’s DDS (trigonometric DDS) presented in 2002. The two layout configurations have been implemented in 90 nm technology and compared in terms of area, speed and power consumption. Comparisons have been performed in terms of circuital complexity on architectures having the same Spurious Free Dynamic Range (SFDR) and phase resolution. Experiments show that the trigonometric architecture is very efficient in terms of area.

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS

This paper describes a digital-mapping direct digital frequency synthesizer having a tuning and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic microwave-integrated circuit (MMIC) is the first solution supporting a sampling rate of 7 GS/s with frequency modulation, phase modulation (PM), and amplitude modulation (AM) in the digital domain. It includes a 14 bits pipelined ripple-carry phase adder and a 10-bits high-speed amplitude multiplier. The minimum frequency, phase, and amplitude steps are 417.2 Hz, 0.022°, and 1.17 mV, respectively. A proof-of-concept chip with an active area of 0.23 mm2 was fabricated in a 1P9M 65-nm CMOS process and characterized in low-profile quad flat package (LQFP). The worst case wideband/narrowband spurious-free dynamic range is 32/42 dBc. This system consumes 85.9 mW/(GS/s) from a 1.2-V power supply when the PM/AM are enabled, resulting in an figure of merit (FoM) of 469.6 GS/ $\text {s}\cdot {2}^{(\mathrm {SFDR}/6)}$ /W. The absolute single sideband phase noise at 100 KHz offset from the carrier was better than −125 dBc/Hz in all the evaluated frequencies. A latency of 12.86 ns was measured when operating at 7 GS/s.