DIRECT DIGITAL FREQUENCY SYNTHESIZER IN THE RESIDUE NUMBER SYSTEM

Oleksiy Polikarovskykh,Lesia Karpova,Vasyl Melnychuk,Ihor Hula

doi:10.47839/ijc.18.3.1523

Abstract

The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

Highlights

An important problem of direct digital synthesis arising in digital systems of frequency synthesis and signals is the speed of processing the values of samples of synthesized signals, the speed of data processing and, in turn, the energy efficiency of such systems
It can be noted that Residue Number System allows for significantly improving the parameters of a computer in a Direct Digital Synthesizers (DDS) in comparison with a computer built on the same physical and technological basis, but in a positional number system, and to receive new more progressive constructive and structural solutions
We considered the ways of designing a digital phase-frequency synthesizer with a phase accumulator in the system of Residue Number System (RNS) and sinusweighted type of DAC

Summary

Introduction

An important problem of direct digital synthesis arising in digital systems of frequency synthesis and signals is the speed of processing the values of samples of synthesized signals, the speed of data processing and, in turn, the energy efficiency of such systems. A permanent storage device replaces a combined device containing an additional interpolator, which allows you to reduce the amount of ROM (Read Only Memory), but leads to increased distortion of the spectrum of the output signal of the digital frequency synthesizer [2]. In any case, to ensure the accuracy of the synthesis of the output frequency, it is necessary to increase the bit rate and the speed of the synthesizer core, which is built on the basis of a cumulative adder. For this purpose, cumulative adders of complex architecture are used, as shown in the work [3]. It was proposed to use non-positional number systems to increase the maximum synthesized frequency with the storage of the digits of the cumulative adder [4]

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Conclusion