A direct digital frequency synthesizer with minimized tuning latency of 12ns

Abstract

A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such updating introduces a rather long carry-ripple. PA lengths of 32-b are commonplace and 48-b or longer PA can be found in commercial DDS products. When a DDS with high data-rate is needed, the long PA carry-ripple can present a serious bottleneck-one usually overcome by some form of PA pipelining-but then, only at the cost of a significant increase in “tuning latency” as well as added power consumption and chip-area. Ref. [1] explains how (for a mere 24-b PA) such pipelining introduces a 55-cycle latency, setting the system's frequency-hopping limit at 700/55 = 12.7MHz, for a DDS generating outputs at 700MHz. All such PA pipelining difficulties are completely eliminated by the architecture reported here.