Digital Frequency Synthesizer Research Articles

A 0.05%–0.08% THD, 762.9 Hz–10 MHz direct digital frequency synthesizer using a reconfigurable DAC for electrochemical impedance spectroscopy measurements

A 0.05%–0.08% THD, 762.9 Hz–10 MHz direct digital frequency synthesizer using a reconfigurable DAC for electrochemical impedance spectroscopy measurements

Research on Implementation of a PWM Generation Algorithm for Train Stationary Stopping Frequency

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far.

A Study on the High Reliability Audio Target Frequency Generator for Electronics Industry

The frequency synthesizer performs a simple function of generating a desired frequency by manipulating a reference frequency signal, but stable and precise frequency generation is essential for reliable operation in mechanical equipment such as communication, control, surveillance, medical, and commercial fields. Frequency synthesis, which is commonly used in various contexts, has been used in analog and digital methods or hybrid methods. Especially in the field of communication, a precise frequency synthesizer is required for each frequency band, from very low-frequency AF (audio frequency) to high-frequency microwaves. The purpose of this paper is to design and implement a highly reliable frequency synthesizer for application to a railway track circuit systems using AF frequency only with the logic circuit of an FPGA (field programmable gate array) without using a microprocessor. Therefore, the development trend of analog, digital, and hybrid frequency synthesizers is examined, and a method for precise frequency synthesizer generation on the basis of the digital method is suggested. In this paper, the generated frequency generated by applying the digital frequency synthesizer using the ultra-precision algorithm completed by many trials and errors shows the performance of generating the target frequency with an accuracy of more than 99.999% and a resolution of mHz, which is much higher than the resolution of 5 Hz in the previous study. This highly precise AF-class frequency synthesizer contributes greatly to the safe operation and operation of braking and signaling systems when used in transportation equipment such as railways and subways.

Development of a high-voltage radio frequency power supply for quadrupole mass spectrometers with a wide dynamic measurement range

The core component of a quadrupole mass spectrometer is the quadrupole mass filter, serving a crucial role in ion analysis. It operates by applying two sets of high-voltage, high-frequency signals with equal amplitude and opposing phases through the radio frequency power supply, capitalizing on variations in the electric field and differences in mass-to-charge ratios to separate incoming ions. This study leverages direct digital frequency synthesis technology and multi-stage voltage amplification techniques to design a tailored radio frequency power supply for quadrupole mass spectrometers with a broad mass range. Practical testing demonstrates that this power supply generates radio frequency high-voltage signals with a peak-to-peak voltage ranging from 2.210 V to 4.220 kV at a resonant frequency of 1.240 MHz, facilitating the separation of ions with distinct m/z values. Furthermore, the radio frequency power supply is integrated into a Self-developed quadrupole mass spectrometer, enabling an assessment of the mass range, resolution, stability of the spectrometer. The results of these assessments confirm that the developed power supply accommodates scanning of m/z value ions in the range of 1 to 1067 while maintaining an absolute resolution of less than m/z = 1 units and an instrument stability of 2.00% over four hours.and keywords.

Real-Time Implementation of a Frequency Shifter for Enhancement of Heart Sounds Perception on VLIW DSP Platform

Auscultation of heart sounds is important to perform cardiovascular assessment. External noises may limit heart sound perception. In addition, heart sound bandwidth is concentrated at very low frequencies, where the human ear has poor sensitivity. Therefore, the acoustic perception of the operator can be significantly improved by shifting the heart sound spectrum toward higher frequencies. This study proposes a real-time frequency shifter based on the Hilbert transform. Key system components are the Hilbert transformer implemented as a Finite Impulse Response (FIR) filter, and a Direct Digital Frequency Synthesizer (DDFS), which allows agile modification of the frequency shift. The frequency shifter has been implemented on a VLIW Digital Signal Processor (DSP) by devising a novel piecewise quadratic approximation technique for efficient DDFS implementation. The performance has been compared with other DDFS implementations both considering piecewise linear technique and sine/cosine standard library functions of the DSP. Piecewise techniques allow a more than 50% reduction in execution time compared to the DSP library. Piecewise quadratic technique also allows a more than 50% reduction in total required memory size in comparison to the piecewise linear. The theoretical analysis of the dynamic power dissipation exhibits a more than 20% reduction using piecewise techniques with respect to the DSP library. The real-time operation has been also verified on the DSK6713 rapid prototyping board by Texas Instruments C6713 DSP. Audiologic tests have also been performed to assess the actual improvement of heart sound perception. To this aim, heart sound recordings were corrupted by additive white Gaussian noise, crowded street noise, and helicopter noise, with different signal-to-noise ratios. All recordings were collected from public databases. Statistical analyses of the audiological test results confirm that the proposed approach provides a clear improvement in heartbeat perception in noisy environments.

R&D of an Innovative OFDM Communication Payload for Small-Size AUV

With its superiorities of low cost, high flexibility and deployment convenience, small-size autonomous underwater vehicles (AUVs) have been extensively applied to perform a variety of undersea missions. While underwater acoustic (UWA) communication provides a practical way to establish a wireless link, it still poses a significant challenge due to the strict limitations of a small-size AUV platform in terms of load capacity, energy supply and cost. Orthogonal frequency division multiplexing (OFDM) has drawn extensive attention due to its high data rate capability and relative robustness to multipath, the performance of which is unfortunately sensitive to the widespread Doppler effect. While efficient Doppler compensation is significantly crucial for UWA OFDM mobile communication, most of the conventional approaches are conducted using software resampling, thus rendering a huge burden on memory and calculation capability as well as a considerable processing delay. In this paper, from the perspective of hardware completion an UWA OFDM communication payload based on STM32F407 processor is designed and implemented to facilitate agile Doppler compensation with low computational overhead. In particular, after estimating Doppler by calculating the time compression or extension of the preamble signal, Doppler compensation is performed by directly adjusting the direct digital frequency synthesizer (DDS)-driven sampling rate of the analog-to-digital converter (ADC). As the Doppler is compensated parallel to the ADC acquisition, processing delay and memory requirement can be avoided. Finally, hardware-in-loop (HIP) simulation is performed to demonstrate the effectiveness and superiority of the proposed system. The results show that the designed system has the potential to achieve an effective communication rate of 3.19 kbps with the admissible implementation overhead. Future work will entail the integration and performance evaluation of the proposed UWA OFDM communication payload on a practical small-size AUV platform.

Measurement and Control System for Atomic Force Microscope Based on Quartz Tuning Fork Self-Induction Probe.

In this paper, we introduce a low-cost, expansible, and compatible measurement and control system for atomic force microscopes (AFM) based on a quartz tuning fork (QTF) self-sensing probe and frequency modulation, which is mainly composed of an embedded control system and a probe system. The embedded control system is based on a dual-core OMAPL138 microprocessor (DSP + ARM) equipped with 16 channels of a 16-bit high-precision general analog-to-digital converter (ADC) and a 16-bit high-precision general digital-to-analog converter (DAC), six channels of an analog-to-digital converter with a second-order anti-aliasing filter, four channels of a direct digital frequency synthesizer (DDS), a digital input and output (DIO) interface, and other peripherals. The uniqueness of the system hardware lies in the design of a high-precision and low-noise digital-analog hybrid lock-in amplifier (LIA), which is used to detect and track the frequency and phase of the QTF probe response signal. In terms of the system software, a software difference frequency detection method based on a digital signal processor (DSP) is implemented to detect the frequency change caused by the force gradient between the tip and the sample, and the relative error of frequency measurement is less than 3%. For the probe system, a self-sensing probe controller, including an automatic gain control (AGC) self-excitation circuit, is designed for a homemade balanced QTF self-sensing probe with a high quality factor (Q value) in an atmospheric environment. We measured the quality factor (Q value) of the balanced QTF self-sensing probes with different lengths of tungsten tips and successfully realized AFM topography imaging with a tungsten-tip QTF probe 3 mm in length. The results show that the QTF-based self-sensing probe and the developed AFM measurement and control system can obtain high quality surface topography scanning images in an atmospheric environment.

Design of Digital Frequency Synthesizer for 5G SDR Systems

The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality.

A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-μm CMOS

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes.

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

<span lang="EN-US">The IEEE 802.15.4 <a name="_Hlk109306810"></a>physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters.</span>

A 2-GHz Two-Tone Direct Digital Frequency Synthesizer

We present a 2-GHz 16-bit direct digital synthesizer (DDS) implemented and verified on a Xilinx Artix-7 FPGA, Nexys-4 DDR development board. The lookup-table based DDS is implemented with the help of multiplexers in a tree structure. The proposed technique can operate at a high clock frequency of 250 MHz and has no truncation error. The proposed DDS is also capable of producing two tones separated by a frequency resolution of 1/1024 times the clock frequency. Further, the tones can be backed off in approximately one dB step from full scale to −96 dB. The back-off is implemented without performing any real multiplication thereby increasing the throughput. 16 such parallel DDS slices are implemented to produce very high-frequency digital sinusoids. The design uses 3095 LUTs, 3465 flip flops, and 18 Block-RAMs for producing two tone output at 2GHz for a given back-off.

An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer.

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.

Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC’s linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.

A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

This paper presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7 psrms integrated over a 100 MHz bandwidth with 28.25 Hz resolution while consuming less than 3 mW at sampling clock 3.12 GHz. The proposed DDFS is fabricated in a 0.9 V TSMC 7 nm CMOS process and occupies a core area of only 0.014 mm.

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

SQUARE-WAVE FREQUENCY MODULATION IN MICROWAVE SPECTROSCOPY

Subject and Purpose. The frequency modulation (FM)combined with lock-in detection, the technique which is used in microwave spectroscopy for enhancing the sensitivity of measurements, as well as the effects due to standing wavesinthe measuring absorption cell can lead to distortions in the spectral line shapes observed. To ensure the highest possible accuracy derivable from the experimental data, these distortions needto be taken into account. A way of improving theaccuracy is to approximate to the experimental line contour with a theoretical line shape that would account for the observable distortion effects.The relevant literature sources suggest examples of theoretical expressions for the line shape in the case of a sinusoidal frequency modulation. This work has been aimed at derivingsimilar expressions for the case of a square-wave frequency modulation that shall allow increasing the accuracy of measurements. Methods and Methodology.The square-wave-FM signalsare obtained with the aid of a direct digital frequency synthesizer thatcan provide switching between two frequencies known to a high accuracy. This technical solution permits generating FM signals with precisely specified parameters. Results. A closed-form expression has been suggested, based on numerically evaluated line shape derivatives, whichallows taking into considerationthe basic types of distortions encountered in the spectral line records. The cases that have been considered concern a variety of experimental conditions, including sub-Doppler measurements with Lamb-dip observations. Conclusions. The approach that has been proposed allows one to properly take into account the distortions of spectral line shapes resulting from the use of a square-wave-FM signal, as well as those due to standing wave effects in the spectrometer cell. As has been found, application of this approach to experimental spectra with a variety of modulation parameters permits reducing the errors of frequency determination to ±0.001MHz, provided the signal-to-noise ratios are reasonably high.

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering

This brief proposes a high spurious-free dynamic range (SFDR) pulse output direct digital frequency synthesizer (PDDS) with low complexity and low power consumption. Independent and uniformly distributed (IUD) high-pass-shaped dither is added to the phase accumulator output, resulting in a wideband spurious-free and low close-in noise floor. The power efficiency and speed are increased by reducing the sampling frequency of the ${m}$ -sequence generator and the high-pass filter (HPF). The SFDR improves by 29 dB as a result of the HPF, which is confirmed with a field-programmable gate array (FPGA) implementation. The application specified integrated circuit (ASIC) occupies $1168~{\mu \text {m}^{2}}$ on nangate 45-nm CMOS process and consumes 80.2 and $398~{\mu }\text{W}$ from a 1.2-V supply with the dither generator running at ${({1}/{4})f_{\text {clk}}}$ and ${f_{\text {clk}}}$ ( ${f_{\text {clk}}}=2$ GHz), respectively.

Adaptive Self-Tuned Controller IC for Resonant-Based Wireless Power Transfer Transmitters

This article introduces an adaptive self-tuned controller IC for resonant wireless power transfer (RWPT) transmitters. The controller IC comprises an on-the-fly very-high-frequency tracking hardware with high resolution and an independent high-resolution digital pulsewidth modulator (PWM)-based (HR-DPWM) current programmed control. These facilitate precise frequency generation as well as adaptive tuning of the reactive components in the matching network, which translate into tight current/power regulation capabilities while retaining optimized power transfer conditions on the transmitting side. The controller IC enables to effectively disengage the power-delivery capabilities from the variations of the resonators, electrical circuits, and wireless medium. The controller core is based on a fully synthesizable digital architecture that has been realized through HDL tools, and several key building blocks have been developed and described in detail: a delay-line-based phase detector, high-resolution digital frequency synthesizer, and HR-DPWM. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, the digital core of the controller has been designed completely through asynchronous architecture, eliminating the need of high-speed clock and its related hardware. The mixed-signal controller IC has been designed, implemented, and fabricated in 0.18-μm 5-V CMOS process, resulting in effective silicon area of 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To demonstrate the mixed-signal controller IC in closed-loop operation of a wireless power system, an experimental 20-W resonant capacitive-based WTP system has been designed and validated. The effectiveness of the controller is well demonstrated and evaluated at the MHz range up to 200 mm misalignment, meeting the strict requirements of resonant-based WPT systems.

Design of sweep frequency signal source in residual stress detection platform based on Zynq

The signal generator based on DDS technology has high frequency and resolution, and is widely used in many fields such as instrument technology, radar, satellite timing, remote control and telemetry, and is one of the important directions of current signal generator research. In order to achieve a cost-effective, high frequency resolution signal source to stimulate the sensors in the residual stress detection system, this paper selects the Zynq-7020 on-chip system to control the 14-bit direct digital frequency synthesis chip AD9954 to obtain a 40Hz~1MHz sinusoidal signal output. Finally, the performance and technical parameters of the system are tested experimentally. The output signal of the signal source is stable, the signal-to-noise ratio is high, and the frequency error is within 0.1%.