Digital Etching Research Articles

Controlled cobalt recess for advanced interconnect metallization

We have developed a wet chemical etch process for the controlled recess of cobalt metal based on ‘digital etching’. Digital etching is a cyclic process wherein each process cycle comprises an oxidation and oxide dissolution step. Due to the self-limiting cobalt oxide thickness, the total recess amount is tuned based on the total number of cycles. This results in nanometer control of the total recess amount as well as excellent within-wafer uniformity. We also evaluated the effect of different oxidation and oxide-dissolution solutions on the cobalt etch amount. Furthermore, the TiN barrier was successfully removed with commodity chemistries without attacking the previously recessed cobalt. This combined process is then used for 10 nm recess of cobalt for the fully self-aligned via (FSAV) advanced interconnect scaling booster. To conclude, we proof the effectiveness of this method by measuring the resistivity of recessed cobalt interconnect lines down to 21 nm.

High-performance InGaAs FinFETs with raised source/drain extensions

In this letter we report on high-performance InGaAs FinFETs with optimized on-off trade-off. The InGaAs FinFETs are fabricated on silicon substrate using a CMOS-compatible replacement-metal-gate process. Excellent off-state performance is achieved by introducing source-drain spacers and doped extension regions. Extensions are fabricated using a digital etching process, a cycling etching technique that allows one to carefully control the position of the junction underneath the spacers. FinFETs with gate length of 13 nm show an on-current of 300 μA μm−1 at VDD = 0.5 V and fixed IOFF = 100 nA μm−1, the highest reported for ultra-scaled Si CMOS-compatible III–V FETs.

Fin-Width Scaling of Highly Doped InGaAs Fins

We study the impact of fin-width scaling on transport in highly doped InGaAs fins and the effect of digital etch (DE). Our experiments suggest the existence of a 10-nm-wide “deadzone” on each side of the fin that does not contribute to the transport. The extent of the deadzone cannot be mitigated by DE nor sidewall passivation. Simulations suggest that the Fermi-level pinning and its associated subsurface depletion region alone cannot explain the relatively wide deadzone that is measured. We propose an explanation based on the combination of Fermi-level pinning and mobility degradation as the fin width scales down. This leads to an apparent wider deadzone than accounted by the Fermi-level pinning alone.

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities.

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

High Uniformity Normally-OFF p-GaN Gate HEMT Using Self-Terminated Digital Etching Technique

A normally-OFF p-GaN gate AlGaN/GaN high-electron-mobility transistor with high ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) uniformity was realized using a self-terminated digital etching technique. ${R}_{ \mathrm{\scriptscriptstyle ON}}$ uniformity control was improved by simultaneously using an AlN etching stop layer in an epitaxial design and a novel digital etching procedure. Digital etching includes the multiple-cycle oxidation and the wet etching of p-GaN layers and provides easy control of p-GaN removal depth and surface damage reduction at the gate-to-drain and gate-to-source spacing areas. Low-frequency noise and pulse measurements indicated that device surface traps and current collapse phenomena were suppressed.

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.

(Invited) High Performance UTB GeOI n and pMOSFETs Featuring HEtero-Layer-Lift-Off (HELLO) Technology

Advanced HEtero-Layer-Lift-Off (HELLO) technology utilizing Ge/SiGe/Ge hetero-epitaxy technique was implemented to realize high quality ultrathin body (UTB) Ge-on-insulator (GeOI) structures. Top interfacial quality of GeOI has been taken care by plasma enhanced ALD-Al2O3 passivation. On the other hand, bottom interfacial quality of GeOI was improved by N2O plasma treatment or Si passivation for UTB GeOI n and pMOSFETs, respectively. Besides, GeOI body thickness (T body) was precisely controlled through SiGe etch stop layer and digital etching process. For lowering parasitic resistance of S/D regions of bulk Ge n and pMOSFETs, ion implantation after germanidation (IAG) has been demonstrated as an effective way. Moreover, high performance UTB GeOI n and pMOSFETs with T body less than 5 nm have been successfully fabricated for the first time. Thickness dependence of carrier mobility of GeOI has also been investigated systematically through split-CV method, revealing a great potential of UTB GeOI structures in future Ge CMOS application.

A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12-nm diameter and has a peak transconductance of 2.6 mS/μm combined with a low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> of 317 Ω·μm, while the p-type exhibits 74 μS/μm. In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive current, 1.8 mA/μm, compared with earlier publications.

Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al2O3-Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

Open circuit potential monitored digital photocorrosion of GaAs/AlGaAs quantum well microstructures

Nanostructuring of semiconductor wafers with an atomic level depth resolution is a challenging task, primarily due to the limited availability of instruments for in situ monitoring of such processes. Conventional digital etching relies on calibration procedures and cumbersome diagnostics applied between or at the end of etching cycles. We have developed a photoluminescence (PL) based process for monitoring in situ digital photocorrosion (DPC) of GaAs/AlGaAs microstructures at rates below 0.2 nm per cycle. In this communication, we demonstrate that DPC of GaAs/AlGaAs microstructures could be monitored with open circuit potential (OCP) measured between the photocorroding surface of a microstructure and an Ag/AgCl reference electrode installed in the sample chamber. The excellent correlation between the position of both PL and OCP maxima indicates that the DPC process could be monitored in situ for materials that do not necessarily exhibit measurable PL emission.

DC and RF Characteristics of Enhancement-Mode Al2O3/AlGaN/GaN MIS-HEMTs Fabricated by Shallow Recess Combined with Fluorine-Treatment and Deep Recess

Enhancement-mode (E-mode) Al2O3/AlGaN/GaN MISHEMTs were fabricated by shallow recess combined with CF4 plasma treatment (SR/F) and deep recess (DR) to compare the effect of each process technique on the device performance. To prevent the device performance degradation induced by plasma damage during gate recess, the digital etch technique was employed. The fabricated E-mode devices have positively shifted threshold voltage, and exhibit lower transconductance (gm) and saturation drain current than depletion-mode devices. Due to the CF4 plasma damage during F-treatment, SR/F shows a sharp drop of gm curve and low saturation drain current. In contrast, DR presents broad gm and high saturation drain current. It is also revealed that the digital etch for gate recess exhibits an isotropic etch profile, consequently increasing the on-resistance. There is no remarkable difference between SR/F and DR in fT and fmax, but DR has a better linearity over SR/F owing to the absence of plasma damage during F-treatment. This results reveal that the DR using digital etch is promising technique to obtain the high performance E-mode MISHEMTs compared to the F-treatment.

A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs

We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl3/SiCl4/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with ${L} _{{g= 20}}$ nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained.

Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching.

Producing densely packed high aspect ratio In0.53Ga0.47As nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III-V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based In0.53Ga0.47As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of InxGa1-xAs is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In0.53Ga0.47As, in contrast to higher bandgap semiconductors (e.g., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In0.53Ga0.47As metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality In0.53Ga0.47As nanostructures that will potentially enable large-volume production of In0.53Ga0.47As-based devices including three-dimensional transistors and high-efficiency infrared photodetectors.

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1]. These devices continue to be the subject of many innovations but face increasing scaling challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing their ultimate scaling limit and being one of the most promising candidates to further support the CMOS roadmap (Fig. 1) [2-5]. In this work, we address some of the challenges faced by these 3D devices, focusing first on the impact of thermal and plasma treatments at gate module [6]. JG and noise can be substantially reduced, without EOT penalty, with a post HfO2 deposition anneal (PDA) and F incorporation in the gate stack by SF6. The latter can also improve the mobility and reduce Nit, mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while also allowing a simplified dual-effective work-function (EWF) metal CMOS scheme where optimized cleans are key. PDA improves the bias-temperature-instability lifetime and hot-carrier immunity via reduction of bulk defects. Furthermore, the doping scheme and EWF metal can also be used to engineer the interface properties. Indeed, improved reliability and LF noise have been reported for junctionless (JL) GAA-NWFETs [4], with SVG.f of inversion-mode (IM) GAA-NWFETs showing more uniform oxide trap density profiles, as a function of depth, for TiAl-based vs. TiN EWF metals [7]. Extensionless IM or JL can also help to enlarge process robustness by ensuring a smaller Eox increase at the bottom-gate edges from the fins release process for lateral GAA-NWFETs formation [4]. These devices are closer to finFETs regarding layout and processing, but vertically stacked lateral NWs will be needed for them to be competitive in performance per footprint, with the drawback of increased parasitic capacitances [3]. Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up new scaling paths by fully using the third dimension [5]. Their gate length is defined vertically and hence can be relaxed without area penalty and used as a knob for variability control and optimized system performance. In this work, we tackle some of the integration challenges in surface definition for these devices, focusing on a channel-first approach. The vertical NWs (pillars) are defined by 193nm immersion lithography followed by dry-etch and wet treatments depending on the channel material employed. For NW doping, up to three stacked layers of (doped) epi are used, requiring pillar etch processes less sensitive to wide doping ranges. For Si NWs, using P doping for NMOS and B for PMOS, an optimized F-based plasma is used to yield arrays of high aspect-ratio pillars with diameters (dNWs) down to ~20nm (from ~42nm after litho). Further dNW reduction can be obtained by applying n cycles of low-temperature [O3-oxidation → oxide etch] for Si-based pillars, digital etch for III-V pillars [8]. Several alternative etch schemes are used for defining the layers surrounding the NWs, overcoming dry and wet etch-layout dependences. A replacement metal gate scheme can enable decoupling the gate module from doping/series resistance optimization for the top part of the pillars, where a highly doped epi layer can be grown for improved contacting (larger contact area). Removal of the dummy gate dielectric from the vertical channel is challenged by the presence of the layer(s) covering the top part of the pillars, selectivity requirements towards the bottom and top isolation layers, and, increasingly so for smaller dNWs, by metrology. A siconi-based oxide etch followed by a wet treatment is used prior to gate stack deposition, with a smoother gate electrode (with W fill-metal) easier to obtain than in a gate-first flow [5].

Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors (HEMTs). High etching-selectivity ratio of InGaAs to InAlAs material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide (H2O2). Selective wet-etching is validated in the gate-recess process of InAlAs/InGaAs InP-based HEMTs, which proceeds and automatically stops at the InAlAs barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAlAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAlAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic transconductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

To achieve low contact resistance between metal and III-V material, transmission-line-model (TLM) structures of molybdenum (Mo) were fabricated on indium phosphide (InP) substrate on the top of an indium gallium arsenide (InGaAs) layer grown by molecular beam epitaxy. The contact layer was prepared using a digital etch procedure before metal deposition. The contact resistivity was found to decrease significantly with the cleaning process. High Resolution Transmission &amp; Scanning Electron Microscopy (HRTEM &amp; HRSTEM) investigations revealed that the surface roughness of treated samples was increased. Further analysis of the metal-semiconductor interface using Energy Electron Loss Spectroscopy (EELS) showed that the amount of oxides (InxOy, GaxOy or AsxOy) was significantly decreased for the etched samples. These results suggest that the low contact resistance obtained after digital etching is attributed to the combined effects of the induced surface roughness and oxides removal during the digital etch process.

Normally-off AlGaN/GaN MOS-HEMT using ultra-thin Al0.45Ga0.55N barrier layer

In this work, we report on the fabrication of a normally-off AlGaN/GaN Metal–Oxide–Semiconductor High Electron Mobility Transistor (MOS-HEMT) using an ultra-thin Al0.45Ga0.55N barrier layer. The AlGaN barrier was thinned down to 1 nm using a digital etching process (Oxidation/Etching) and was followed by a PECVD deposition technique of a 7 nm thick SiOx layer used as gate insulator. Thanks to the thin AlGaN barrier layer (4 nm), only a few digital etching cycles are required to shift the threshold voltage toward positive values. The fabricated normally-off device exhibits a pinch-off voltage of +1.1 V, a maximum IDS current of 460 mA mm−1 at VGS = +5 V, an On-state resistance (RON) of 7.8 Ω · mm and an ION/IOFF ratio higher than 109. Moreover, the pulsed IDS–VDS and capacitance–voltage (C–V) curves versus frequency confirm that there is no damage induced by the digital etching process.

Digital Etch Technique for Forming Ultra-Scaled Germanium-Tin (Ge1\u2212xSnx) Fin Structure

We developed a new digital etch process that allows precise etching of Germanium or Germanium-tin (Ge1−xSnx) materials. The digital etch approach consists of Ge1−xSnx oxide formation by plasma oxidation and oxide removal in diluted hydrochloric acid at room temperature. The first step is a self-limiting process, as the thickness of oxide layer grows logarithmically with the oxidation time and saturates fast. Consistent etch rates in each cycle were found on the Ge1−xSnx samples, with the surfaces remaining smooth after etch. The digital etch process parameters were tuned to achieve various etch rates. By reducing the radio frequency power to 70 W, etch rate of sub-1.2 nm was obtained on a Ge0.875Sn0.125 sample. The digital etch process was employed to fabricate the Ge1−xSnx fin structures. Extremely scaled Ge0.95Sn0.05 fins with 5 nm fin width were realized. The side walls of the Ge0.95Sn0.05 fins are smooth, and no crystal damage can be observed. This technique provides an option to realize aggressively scaled nanostructure devices based on Ge1−xSnx materials with high-precision control.

Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter

This letter introduces a novel alcohol-based digital etch technique for III-V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides.

MBE growth and digital etch of GaSb/InAs nanowires on Si for logic applications

The 6.1 Å III–V “high-mobility” semiconductor family includes materials with beneficial transport properties of both electrons and holes (InAs, GaSb), which are appealing for fast and low-power complementary metal–oxide–semiconductor applications. Yet their large lattice mismatch with Si (∼12%) results in three dimensional island nucleation and therefore growth defects. The solution for deposition of this high mismatch material is the growth of the entire device from a single nucleus, such as in vertical nanowires. Two types of GaSb nanowires (NWs) are demonstrated on a Si(111) substrate: vertically stacked InAs/GaSb NWs and coaxial core/shell NWs. This paper summarizes surface preparation, growth conditions, and postprocessing steps which can be used to create nanowires with small enough diameters for use as logic devices.