MBE growth and digital etch of GaSb/InAs nanowires on Si for logic applications

Abstract

The 6.1 Å III–V “high-mobility” semiconductor family includes materials with beneficial transport properties of both electrons and holes (InAs, GaSb), which are appealing for fast and low-power complementary metal–oxide–semiconductor applications. Yet their large lattice mismatch with Si (∼12%) results in three dimensional island nucleation and therefore growth defects. The solution for deposition of this high mismatch material is the growth of the entire device from a single nucleus, such as in vertical nanowires. Two types of GaSb nanowires (NWs) are demonstrated on a Si(111) substrate: vertically stacked InAs/GaSb NWs and coaxial core/shell NWs. This paper summarizes surface preparation, growth conditions, and postprocessing steps which can be used to create nanowires with small enough diameters for use as logic devices.