Digital Down Converter Research Articles

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

A real time digital vibration acceleration fiber sensing system based on a multi-carrier modulation/demodulation technique

A multi-longitudinal mode fiber laser sensor (MLMFLS) system based on digital modulation/demodulation technique for vibration acceleration detection is proposed. To the best of the authors’ knowledge, this is the first digital vibration acceleration demodulation system ever reported by a MLMFLS system. A few beat frequency signals (BFS) generated by the MLMFLS are used as signal carriers of applied vibration signals. Based on multi-channel digital down-conversion technique, the weak vibration signals modulated on the BFS are superposed by utilizing the digital universal software radio peripheral (USRP). The signal-to-noise ratio (SNR) of the output vibration signal is greatly enhanced. A spectral subtraction method is also utilized to improve the SNR of the demodulated vibration signal. The acceleration of the vibration signal is obtained after second order differential of the time domain vibration signal. By simply changing the position of window function of short-time Fourier transform, a real-time vibration frequency and acceleration sensing system is achieved. The measurement results demonstrated a minimum detectable acceleration of 0.03 g at vibration frequency of 1.0 Hz by the designed sensing system. It also has a simple structure, high signal-to-noise ratio and stability.

Research on an Active Hydrogen Maser Digital Circuit Control System Based on FPGA.

A hydrogen maser is a high-precision time measurement instrument with high frequency stability and low frequency drift, which is widely used in satellite navigation, ground time keeping, frequency measurement, and other fields. An active hydrogen maser (AHM) is better than the current space passive hydrogen maser (PHM) in orbit in terms of its frequency stability and drift rate, but it has the disadvantages of large volume and weight. To further reduce the volume and weight of the circuit, this paper demonstrates a digital circuit control system based on a field-programmable gate array (FPGA). It uses digital temperature control, digital detectors, digital down-conversion, digital phase-locked loops, and other digital methods for temperature control, cavity auto-tuning, and crystal phase locking, which improve the integration and flexibility of the circuit system. Meanwhile, a tuning method based on hydrogen flow is proposed, which effectively solves the problem of fluctuations in hydrogen maser resonance frequency with changes in the external environment. Our experimental results show that the designed digital circuit control system meets the requirements of an oven-controlled crystal oscillator (OCXO) loop and a cavity loop. Its frequency stability can reach 2.6×10-13/1 s and 1.4×10-15/10,000 s, which is close to the stability index of ground active hydrogen maser. This scheme has certain practical engineering value, and can be used in the design of hydrogen masers for next-generation space navigation satellites, deep space exploration, and space stations.

Design of Intelligent Channelizer for Extracting Signals of Arbitrary Centre Frequency and Bandwidth

There are two standard approaches to the problem of wideband signal channelization, namely those based upon the use of a digital down conversion (DDC) unit and those based upon the use of a polyphase discrete Fourier transform (DFT) or PDFT. There are clear advantages and disadvantages with both approaches, however, in that: a) with the DDC approach, optimal performance and flexibility is obtained but at the expense of a heavy computational load; whereas b) with the PDFT approach, a sub optimal and less flexible performance is obtained but at a greatly reduced computational cost through the exploitation of a suitably defined fast Fourier transform (FFT). An intelligent channelizer is described herein which possesses a flexible design able to exploit the merits of both approaches for the case where the input data comprises real-valued samples. The two key design features are: a) optimal setting of the PDFT parameters to ensure that for every signal of interest there is at least one channel completely containing it; and b) simultaneous computation of two real-data FFTs: the first as required by the PDFT and the second, a high-resolution FFT with high update rate, able to accurately direct the application of the low-rate DDC units to the relevant PDFT channel outputs.

A 94 GHz Pulse Doppler Solid-State Millimeter-Wave Cloud Radar

A 94 GHz pulse Doppler solid-state millimeter-wave cloud radar (MMCR), Tianjian-II (TJ-II), has been developed. It reduces the size and cost using a solid-state power amplifier (SSPA) and a single antenna. This paper describes the system design, including hardware and signal processing components. Pulse compression, segmented pulse, and dual pulse repetition frequency (PRF) technologies are employed to overcome the limitations imposed by the low power of the SSPA and the high frequency of 94 GHz. The TJ-II also features a dual-polarization, high-gain antenna for linear depolarization ratio detection and a time-division receive channel to improve channel consistency and save on costs. To achieve high flexibility and low interference in signal transmission and reception, the TJ-II uses software-defined radio technology, including direct digital synthesis, digital downconversion, and bandpass sampling. A series of Doppler power spectrum processing methods are proposed for detecting weak cloud signals and improving scene adaptability.

Multiple Signal TDOA/FDOA Joint Estimation with Coherent Integration

Passive localization relies significantly on the estimation of the Time Difference of Arrival (TDOA) and Frequency Difference of Arrival (FDOA) to accurately determine the location of a target. The precision of TDOA and FDOA estimation is affected by signal parameters of time and frequency distribution. In case of multiple signals arising at different frequency bands and intercepted simultaneously by spatially separate sensors covering a wide frequency band, the traditional method is first to separate the signals from the mixed wideband signal through digital down conversion (DDC), which brings multiple narrowband signals, and then the estimation of TDOA and FDOA of each narrowband signal can be performed using cross ambiguity function (CAF). The paper introduces a novel approach for estimating TDOA and FDOA of multiple signals simultaneously, which employs a coherent integration method. First, the cross ambiguity function for each signal is realized with the narrowband signal as the same as the traditional method. Next, the phase relation of each CAF is analyzed, then the joint CAF can be obtained with phase compensation, from which multiple signal TDOA and FDOA estimations will be implemented simultaneously. Numerical simulations are performed to compare the two methods, and the results demonstrate the superiority of the proposed algorithm.

Implementation of polyphase digital down converter for wireless applications

This paper briefs the hardware-efficient polyphase digital down converter (DDC), which reduces the input sampling frequency to 3.64 GHz and produces a complex output to meet the IEEE 802.11ah wireless network standard. The design comprises a polyphase mixer (PM) filter and a lowpass polyphase finite impulse response (PFIR) filter. The PM filter uses a cascaded integrator comb (CIC) decimation filter based on multiplexer technology to potentially process parallel input interfaces and considerably reduce the sampling rate. The time-sharing mechanism of the CIC filter performs an efficient hardware implementation. Again, the improved design technique of the PFIR filter can effectively increase the operating speed and optimize power consumption. The proposed design offers high flexibility due to programmable sampling rate factors that can support multistandard communication systems. In addition, the design includes the truncation mechanism to protect against overflow errors and the fixed-point data type in each filter node to minimize the area requirements. The presented polyphase DDC is tested using the field-programmable gate array (FPGA) platform targeting the Xilinx Kintex-7 device. According to experimental results, the described DDC significantly reduces the logical resources and power dissipation associated with earlier design structures. The functional verification is tested to ensure the validation of the suggested design.

Optimal equivalent‐time sampling for periodic complex signals with digital down‐conversion

AbstractEquivalent‐time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down‐conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in‐phase/quadrature gain imbalance instead of requiring a high‐speed analog‐to‐digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent‐time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent‐time sampling using DDC.

Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.

A 2.0 GS/s Two-Stage Quad-Channel Digital Downconverter for a 380 GHz Spaceborne Atmospheric HO Monitoring Instrument

This brief presents a quad-channel 2.0 GS/s digital downconverter (DDC) chip in 65nm CMOS that supports the NASA Stratospheric Water Inventory and Tomography by Convective Hydration (SWITCH) spaceborne instrument. The presented DDC chipset provides a wide input bandwidth and allows the transmitted 380 GHz signals to be channelized to perform the atmospheric measurements. The prototype DDC chip is implemented in a 65nm CMOS technology and consumes 177mW of DC power.

A real-time phase processing system for phase sensitive optical time domain reflectometer.

In order to improve the real-time performance of a phase-sensitive optical-time-domain reflectometer (Φ-OTDR), a fully digital phase processing system is demonstrated. Using digital down-conversion and field programmable gate array (FPGA) hardware calculation, the phase of the Rayleigh scattering light can be demodulated in real-time. Benefiting from the pipeline calculation in the FPGA, the real-time performance of this system is not affected by the interrogation rate and fiber sensing distance. Experiments show that this real-time detection system has the same vibration detection performance as an offline data process and has good stability. The dynamic strain sensing with a sensing distance of 50 km, an interrogation rate of 1kHz, and a spatial sampling interval of 1m is experimentally demonstrated. The obtained results indicate that the fully digital signal processing system can ensure the real-time detection of Φ-OTDR under the condition of long distance and high resolution.

Digital Post-processing Techniques for Time-interleaved ADCs

This paper presents an all-digital post-processing circuit for a high-speed and high-precision time-interleaved ADC (TIADC). By pre-inputting a test signal in the TIADC, channel mismatch errors are estimated and stored, and the stored values are extracted to compensate for errors when the input signal is at a special frequency. The frequency can be detected by a threshold judgement module. This solves the problem of the traditional modulation calibration algorithm, which cannot calibrate the signal at a special frequency. A high-speed low-complexity digital down converter (DDC) circuit with an optional decimation ratio of 1, 2, 4, or 8 times was designed to have different frequency outputs of the TIADC. We applied it to a four-channel 14-bit 360-MHz TIADC system with an input signal fin of 110 MHz. The FPGA verification results show that after calibration and decimation, the spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) improve by about 40 dB and 30 dB, respectively.

FPGA Implementation of Polyphase Digital Down Converter for WiMAX Systems

ABSTRACT This paper briefs the implementation of a reconfigurable digital down converter (DDC) on a field-programmablegate array (FPGA) development board to be used in worldwide interoperability for microwave access (WiMAX) applications. The proposed polyphase design includes a parallel number of coordinate rotation digital computer (CORDIC) processors and low-passfinite impulse response (FIR) filters. Furthermore, the single rate FIR filter works with complex data input using canonical implementation. This strategy reduces multiplications and computational complexity. Additionally, the sample rate factor can be dynamically reconfigured to support multistandard DDC architectures. The mathematical expressions of the proposed design are briefly described. Comparison results indicate that the proposed design saves the hardware resources to achieve a cost-effectivesolution for software-definedradio standards. The simulation and experimental results are used to verify the correctness and feasibility of the polyphase DDC structure.

Implementation of real-time high-speed ultrasound communications through tissue

In this work, we propose a novel implementation of both a transmitter and receiver with field programmable gate arrays (FPGAs) to achieve real-time continuous high-definition (HD) video transmission through tissue, which can enable HD and higher frame rate wireless capsule endoscopy. We used a Texas Instruments AFE58JD48EVM 16 channel analog front end (AFE) evaluation board as the receiver connected to a Xilinx ZCU106 Zynq Ultrascale MPSoC development board in which we implemented a digital down converter (DDC), OFDM demodulator, maximum ratio combiner and low-density parity-check (LDPC) decoder. For the transmitter, we used an Analog Devices EVAL-AD9166 vector signal generator evaluation board, which has a built-in 4.3 dBm output power amplifier as a transmitter connected to another ZCU106 development board in which we implemented a LDPC encoder, OFDM modulator and digital up converter (DUC). The modulated signal was transmitted through a tissue-mimicking abdominal phantom using a 2-mm microcrystal transducer and received with a Sonic Concepts IP103 64 channel phased array at a center frequency of 3.2 MHz. We achieved the continuous transmission of up to over[OML1] 6 Mbps error free payload data rate after LDPC decoder which is used to carry HD video streams through ultrasound.

A time-interleaved ADC calibration technique for spectrum monitoring applications

A fully background estimation and calibration technique to reduce the spur powers caused by time-interleaved ADC architecture is presented. The estimations of mismatches are succeeded using easily generated calibration signals. The implementation details for the mismatch estimations and calibrations are provided using a 2.8 GSPS ADC and a FPGA device. Continuous operation of the spectrum monitoring applications is allowed while the mismatch estimation and the calibration process in progress. The offset mismatch calibration is realized using an adder circuit at the background and more than 10 dB spur power reduction is obtained from the proposed method. A digital multiplier circuit is used to realize the gain calibration. The timing skew calibration is fulfilled by the addition of a small offset to the DDS (Direct Digital Synthesizer) phase offset of DDC (Digital Down Converter). It is possible to get more than 6 dB power reduction at some critical spur signals after the application of proposed timing mismatch calibration technique when a single tone sine wave input is applied.

Area and power-efficient reconfigurable digital down converter on FPGA

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

Design and implementation of HF signal receiving and processing module based on FPGA

This article designs and implements a receiving processing module based on the Xilinx ZCU102 evaluation board for the signal waveform defined in Appendix C of MIL-STD-188-110C. The focus is on the digital down-conversion, synchronization capture, and adaptive equalization algorithm for this signal processing module. Compare and design two adaptive algorithms, LMS (Least Mean Square) and DLMS (Delayed Least Mean Square). LMS algorithm has better convergence effect than DLMS algorithm, and the calculation efficiency is lower than the DLMS algorithm based on the structure of the systolic array. The signal waveform is tested under CCIR (International Radio Consultative Committee) HF (High Frequency) channel. The experimental results show that the receiving processing module has good feasibility for signals under medium HF channels.

Multifunctional Digital Backend for Quasar VLBI network

The new 13-meters radio telescope recently built at Svetloe observatory (Russia) required a backend device that could digitize wideband signals from the receiving system, process the signal appropriately, prepare and transmit the resulting signal to the recorder. The previously existing backends, also used at other radio telescopes of Quasar VLBI network, could not provide compatibility with VGOS (VLBI Global Observing System) requirements. We developed Multifunctional Digital Backend (MDBE) with superior performance, flexibility and functions to equip the new antenna and other radio telescopes of the network with the same backend compatible with both domestic and international systems. The MDBE contains up to 12 input channels with 2 GHz bandwidth, powerful and remotely configurable Field programmable gate arrays (FPGA) for digital signal processing, and optical transceivers with total throughput of 50 Gbps per channel. The digital downconverters implemented in FPGA can form sub channels with 0.5, 2, 4, 8, 16, and 32 MHz bandwidth freely tuned with 10 kHz step. In wideband mode a single channel with 512, 1024 or full 2048 MHz bandwidth can be recorded. The MDBE also supports single-dish applications, such as radiometric and spectrometric observations. The paper presents the results of hardware and firmware development of the system, and the experimental results received with the MDBE in Svetloe observatory.

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

Multi-longitudinal mode fiber laser digital vibration-sensing system based on a multi-carrier modulation/demodulation technique.

A multi-longitudinal mode fiber laser sensor (MLMFLS) system based on a digital modulation/demodulation technique is proposed. To the best of the authors' knowledge, this is the first digital vibration-demodulation system ever reported by a MLMFLS system. Multiple beat frequency signals (BFS) generated by the MLMFLS work as signal carriers of applied vibration signals. The vibration signals modulated on several BFS at different frequencies are simultaneously demodulated based on a multi-channel digital down-conversion technique by utilizing the digital universal software radio peripheral (USRP). The demodulated vibration signals from different signal channels are superposed by the USRP. Signal-to-noise ratio (SNR) of output vibration signal is highly improved, which increases sensing stability and accuracy of the system. This is really important for sensing of vibration signals that have an extremely low frequency or weak energy. Measurement results demonstrate that the sensing system has an excellent low frequency vibration-sensing capability, simple structure, high SNR, stability and accuracy.