Design and implementation of HF signal receiving and processing module based on FPGA

Abstract

This article designs and implements a receiving processing module based on the Xilinx ZCU102 evaluation board for the signal waveform defined in Appendix C of MIL-STD-188-110C. The focus is on the digital down-conversion, synchronization capture, and adaptive equalization algorithm for this signal processing module. Compare and design two adaptive algorithms, LMS (Least Mean Square) and DLMS (Delayed Least Mean Square). LMS algorithm has better convergence effect than DLMS algorithm, and the calculation efficiency is lower than the DLMS algorithm based on the structure of the systolic array. The signal waveform is tested under CCIR (International Radio Consultative Committee) HF (High Frequency) channel. The experimental results show that the receiving processing module has good feasibility for signals under medium HF channels.