Digitally Controlled Oscillator Research Articles

Analysis of Frequency-Aid Technique for Fractional-N Digital BB-PLLs in Time-Domain

This brief make an original analysis of the frequency-aid technique using ternary phase detectors (TPDs) for fractional-N digital Bang-Bang (BB) phase-locked loops (PLLs). We prove that the minimum value of the TPD dead-zone to prevent a limit-cycle happening in the BB-PLL, in fact, can be reduced by a factor of 28 when using a novel mathematical expression, for a reference signal with -155 dB noise floor. Furthermore, we show that increasing the gain of the integral path tuning the digitally-controlled oscillator coarse bank does not guarantee a faster locking as typically believed. Finally, this brief proposes closed-form expressions for the TPD dead-zone and the gain of the additional proportional path to minimize the transient time.

112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels

A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, −35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.

An E‐band digitally controlled oscillator with effective tuning bank

AbstractAn E‐band digitally controlled oscillator (DCO) with effective tuning bank is presented and fabricated in 40 nm CMOS technology. The DCO is promoted with an effective fine tuning bank based on a binary‐weighted switched capacitors array connected with the secondary coil of an effective flipped stacked transformer with weak mutual coupling factor to improve the tradeoff relationship among tuning range, circuit complexity and frequency resolution. The measured best fine tuning step of the DCO is 2.21 MHz. The operating frequencies range of the DCO covers from 76.61 to 84.51 GHz. The DCO also achieves a figure of merit normalized for area (FoMA) of −185.1 dBc/Hz.

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC -based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of −104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times $ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm2 and consumes 40 mW.

RETRACTED: A wide range high resolution digital controlled oscillator with high precision time to digital convertor for optimal sampling digital PLL

Abstract The rapid growth of wireless communication structure makes the vitality of front line circuit at wide range, high targets and exactness concern. Such pushed circuits for electronic banner arranging are refreshing in supportive state for wide range applications. All digital phase locked loop (ADPLL) is goliath part in transmitter and recipient in remote correspondence. In ADPLL, the digital controlled oscillator (DCO) and time to digital controller (TDC) is the essential squares. In light of the poor stage impact of DCO, the ADPLL isn't reasonable for current wide range remote structures. The goals issue in TDC can impacts the ADPLL execution by lacking and non-linearity. For wide range applications, we propose an Optimal Sampling Digital PLL utilizing wide Rage high Resolution DCO and high Precision TDC, named as R2POS-DPLL. The proposed no ifs ands or buts controlled oscillator contains bootstrapped ring oscillator which gives reinforced section voltage swing to invigorate driving most remote point. A pushed circuit structure is utilized to overhaul linearity of a sub-district delay in TDC, without requiring tight essential exactness and a key number of parts. In addition, the blend of DCO and TDC what's more fortifies the execution of ADPLL and make fitting for IoT applications. The proposed R2POS-DPLL setup is executed in Xilinx contraption with various FPGA families. The results proved that the proposed method is effective in terms of power consumption, frequency resolution, hardware utilization and locking range, etc.

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is 1800 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 1.233 K gate count. The RMS current consumption is 103.32 μA from 1 V voltage supply with 103.32 μW power requirement. The experimental results reveal, DCO draws 480 μA current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOMT at 1-MHz offset frequency from 2.44 GHz carrier frequency are -122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively.

A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET

All-digital PLLs (ADPLLs) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLLs) do not exhibit quantization noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain to cover frequency drift due to temperature variations. Further, in CP-PLLs, the reset pulse of phase detector (PD) must be wide for proper PLL functioning, but this sets a lower limit on reference spurs. We propose a hybrid-PLL in a 7-nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL. We introduce periodical phase realignment by the reference clock, and ultrashort pulse for resetting the PD. The hybrid PLL covers 0.2–4 GHz and settles in 0.6 us. It emits low −52 dB reference spurs in the conventional mode, and 1.05 ps and 0.62 ps integrated jitter in the conventional and realignment modes, respectively.

A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control

An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. The reference spur of the proposed PLL is −78 dBc.

DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

A 30mV input battery-less power management system

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster.

A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.

Design and Simulation of Low Power Consuming Digital Controlled Oscillator in All Digital Phase Locked Loop

Recent IC technology innovations can achieve lowpower biomedical implant functionality.RF transceivers require low-power and small-sized components in biomedical implants to achieve the best results in frequency and phase control. Phase Locked Loop (PLL) is the key component for controlling these parameters in low power consumption RF transceivers. Therefore All Digital Phase Locked Loop (ADPLL) is chipping effectively into a major role in the fields of Biomedical &amp; Communication. ADPLLs contribute better results in these areas due to their efficient blocks. This paper focuses on the design of low-power Digital Controlled Oscillator (DCO) and provides information on the various ADPLL blocks. To reduce power dissipation DCO is designed with XNOR gate using delay elements by avoiding direct contact between VDD &amp; GND and the MOS transistors were arranged in ring topology. Tanner tools were used to design and simulation. In addition to this it also provides the detailed history of PLLs &amp; ADPLLs and their mathematical analysis. Compared to previous design, the current DCO design gives better power consumption results.

A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar

In this paper, the optimized design strategies for the implementation of a CMOS digitally controlled oscillator (DCO) are investigated. Moreover, the boosting mechanism for a DCO with and without negative resistance is considered. The proposed design methodology is based on an in-depth mathematical analysis of the startup condition and amplitude of oscillation. This approach results in an optimized topology for a Colpitts Clapp-DCO (CC-DCO). The improved performance is achieved through the negative resistance boosting mechanism. The negative resistance enhances the startup time and increases amplitude stabilization across a wide tuning range (TR). Moreover, it improves the phase noise (PN) performance while suppresses the amplitude-to-phase conversion. The proposed 24-GHz CMOS enhanced CC-DCO (ECC-DCO) is implemented in 65-nm TSMC CMOS process. It can effectively reduce the startup time by 41%. Also, it boosts and stabilizes the amplitude across a TR of 29%. The amplitude varies by 1.5% across the 22-29-GHz TR. The ECC-DCO consumes 12.8 mW. It shows a PN of -106 dBc/Hz at 1-MHz offset frequency and achieves -185-dBc/Hz figure of merit (FoM) and -194-dBc/Hz FoM for tuning.

A 243-mW 1.25–56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

This article presents a compact analog-to-digital converter (ADC)/digital-to-analog converter (DAC) digital signal processing (DSP)-based long reach (LR) transceiver in 7-nm FinFET technology that operates seamlessly from 3.5—56 Gb/s in pulse-amplitude modulation (PAM-4) [from 1.25 to 28 Gb/s in non-return to zero (NRZ) mode] and consumes only 243 mW at 56 Gb/s. The receiver (RX) front end consists of a two-stage continuous-time linear equalizer (CTLE), a 40-way time-interleaved (TI) successive approximation register (SAR)-ADC, a DSP equalizer containing a 17-tap feed-forward equalizer (FFE) working concurrently with a one-tap speculative decision feedback equalizer (DFE) and a reflection canceling FFE, which implements four individually roaming taps. Clock recovery is achieved on a dedicated low latency path consisting of a five-tap FFE, slicer, time error detector (TED), and loop filter driving a dedicated LC —digital-controlled oscillator (DCO). The transmit section consists of a variety of pattern generators, a five-tap finite impulse response (FIR) section, and a terminated DAC as an analog transmitter. When working on a 42.5-dB-LR channel at 56 Gb/s PAM-4, the transceiver consumes 243 mW from the 0.9-V (analog) and 0.75-V (digital) supplies, corresponding to an efficiency of 4.3 pJ/b.

A Supply-Noise-Insensitive Digitally-Controlled Oscillator

A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-triode combination in conjunction with a weak latch to mitigate the supply sensitivity of inverter-based delay cells and remain supply noise insensitive over a wide range of supply variation. A proof-of-concept prototype for the DCO in 65 nm-CMOS process occupies $90\times 210\,\,\mu \text{m}\,\,^{\mathrm{ 2}}$ area and consumes 2.25 mW operating over a range of 0.9–1.4 GHz output frequency. At 850 Mv-supply voltage, the frequency pushing of DCO is zero at the optimal point and remains less than 10% over a large excursion of 50 mVpp. When embedded into an all-digital phase locked loop, closed-loop measurements demonstrate that supply noise with 50 mVppmagnitude does not impact the loop dynamics.

A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TDC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption was 6.0 mW.

Design an All Digital PLL with Ripple Reduction Technique

The article describes about the design and implementation of advance version of Phase Lock Loop (PLL) is All Digital PLL. Research work is on ADPLL where parameter ripple is reduced by applying the technique of ripple reduction technique. Ripple reduction technique reduces the use of Kth counter, Kth counter comes under consideration when enable is ON. Phase locked loops are most widely used in communication system. Most of the PLL’s that are used currently are hybrid type PLL’s where all the blocks are assumed to be digital. The circuit design of ADPLL consists of Digital Controlled Oscillator (DCO), loop filter and Phase Frequency detector (PFD). Here phase detector used is Ex-or gate, for loop filter, Kth counter is used and Increment/Decrement circuit is used as DCO. Divide-by-N counter is used for feedback system. The output of the DCO is going in the PFD through the feedback network. Xilinx Vivado suit 2018.2 tools is used for simulating Verilog code. Board chosen in vivado is zed board Zynq. First, with the help of circuit diagram of ADPLL Verilog code is being written on project window. After compilation of code it is simulated with the help of test bench. After that it is going to be implemented and verified with the board zedboard. Number of LUTs used are 32 and Flip Flops used are 35. This paper presents an all digital approach for the design, simulation, synthesis and implementation of FPGA based ADPLL centered at 195.31 KHz using Verilog HDL code. The proposed design methodology resulted in reduction of ripple, power dissipation, junction temperature of board. Proposed research work further can be used in communication for frequency synthesizer. Any system whether it is from communication or digital etc ADPLL is common to use for ripple reduction at its output. So ADPLL is basic building block in any type of communication system.

Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning

This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage (Vdd). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with Vdd of 1.8 V. Effect of Vdd variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with Vdd variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with Vdd variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz.

A low-power reference-less clock/data recovery for visible light communication devices requiring low data throughput

In this study a reference-less clock and data recovery (CDR) is designed and developed for the low speed visible light communication system based Internet of Things (IoT) tags. Design system incorporates an off-chip photodiode and an integrated-on chip front-end receiver with the reference-less CDR. For an IoT tags low power consumption, low supply voltage, and small area are the major design constraint. Considering these constraints, the circuit of the front-end receiver incorporate the near-threshold cascode current mirror based transimpedance amplifier, low pass filter and a comparator. On the other-hand, low power all-digital phase locked loop-based reference-less CDR is design herein with a modified loop filter, auto tune digital control oscillator and auto duty cycle adjustment circuit. The circuit is implemented in an integrated chip with area of 0.728 mm2 via TSMC 180 nm process. Experimental measurement results of the tapeout chip shows that the phase noises are − 39.54 dBc/Hz @ 1 kHz, − 80.35 dBc/Hz @ 10 kHz and − 92.26 dBc/Hz @ 100 kHz. The measured jitter in the recovered clock is 3.312 ns (0.0033 UI). At 1 Mbps, the measured total power consumption is 5.58 μW. The achieve results shows that the implemented circuit in this study highly support the commercial low data rate based optical wireless sensing nodes for IoT tags.

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

In this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save ~50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the second harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11-dBm output with < −55-dBc HD2. The 1.8-GHz DCO exhibits −116-dBc/Hz phase noise (PN) at 1-MHz offset and draws 195 uW from 0.3-V supply. The error vector magnitude measured with a 2-MHz 64-Quadratic amplitude modulation (QAM) orthogonal frequency division multiplexing signal at 5-dBm average power is 3.7%.