Abstract
This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.
Highlights
The development of low-power applications, such as the Internet of Things [1], Energy Harvest [2], Intra-Body Communication systems [3], and the Wireless Sensor Network (WSN) [4,5], has spurred the research on low-power design
The WSN system lifetime is still limited by the large power consumption of its radio, especially the phase-locked loop (PLL) that performs as a local oscillator and provides high-frequency accuracy and low phase noise
We proposed a multi-stage capacitance shrinking (MACK) technique for low-voltage and low-power digitally controlled oscillator (DCO)
Summary
The development of low-power applications, such as the Internet of Things [1], Energy Harvest [2], Intra-Body Communication systems [3], and the Wireless Sensor Network (WSN) [4,5], has spurred the research on low-power design. The WSN system lifetime is still limited by the large power consumption of its radio, especially the phase-locked loop (PLL) that performs as a local oscillator and provides high-frequency accuracy and low phase noise. To reach the performance of the counterparts in CPPLLs, i.e., the voltage-controlled oscillators (VCOs), the oscillator in [14] used a nine-bit digital-to-analog converter (DAC) to convert the digital frequency control words (FCW) to analog signals that were fed to a VCO It had a very high resolution, the added DAC multiplied the burdens of power consumption and area. The LC-DCO based on a cross-coupled structure achieved a more superior phase noise performance than ring oscillators. A multi-stage capacitance shrinking (MACK) technique was proposed to form the LC tank, which largely improved the resolution of the ∆Σ-less DCO without increasing the power consumption of the chip.
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