Digitally Controlled Oscillator Research Articles

Automated design flow for synthesizable ADPLL: From specification to GDS

We propose an automated design flow for an all-digital phase-locked loop (ADPLL) that selects and implements a PLL layout that satisfies user given input specifications using place-and-route (PnR) tools within 1.2 h. The all-digital architecture enables the use of a theory-based frequency domain model for predicting the output specifications once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterize the effective current to capacitance ratio from only 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows an error rate less than 1.5 % for estimating frequency range and power consumption. The generator guides the user to a feasible set of specifications using the analytical model by providing the achievable range of the failed specification. As design examples, 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65 nm CMOS process.

Design and analysis of high-resolution CMOS digitally controlled oscillator with tunable transformer

A tunable transformer based millimeter-wave digitally controlled oscillator (DCO) is proposed to achieve high frequency resolution with compact area in this paper. An 8-shaped inductor is employed as primary coil of the transformer to generate the opposite magnetic field and achieve a weak coupling to the secondary coil, which is beneficial to enhance the scaling effect of the capacitor to achieve a smaller equivalent capacitance. The equivalent model of the transformer structure is analyzed theoretically. Distributed capacitors are placed under the secondary coil, which can be flexibly adjusted to achieve high frequency resolution. A digitally controlled artificial dielectric (DiCAD) differential transmission line is implemented to achieve coarse and medium frequency tuning. The DCO is implemented in 40-nm CMOS process with a core area of 0.026 mm2. Simulated results demonstrate a minimum frequency tuning step of 381 KHz with a frequency tuning range of 12.3% from 58.60 to 66.28 GHz, and the phase noise at 1-MHz offset is from −91.3 to −94.0 dBc/Hz, corresponding to an FoM range of −179.5 to −182.2 dB, while the power consumption is 8.8 mW.

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

SummaryA high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2.

A Digitally Controlled Oscillator for ADPLL using combinational frequency multiplier and novel variable delay inverter

In this article, a novel digitally controlled Oscillator (DCO) for All Digital Phase Locked Loop (ADPLL) is presented. In the proposed DCO, the concept of a combinational frequency multiplier is used to double the frequency range of a conventional digital ring oscillator. However, conventional combinational frequency multiplier circuits can produce a 50% duty cycle only for a single input frequency. Hence, a novel circuit for frequency multiplication is proposed that can produce an output frequency equal to 2 times the input frequencies with a 50% duty cycle for all the frequencies. The proposed DCO is developed by integrating a digitally controlled ring oscillator with the proposed novel combinational multiplier. Digitally controlled delay inverters are used to design both the DCRO and the novel combinational frequency multiplier. A 5-bit DCO is realized using a 4-bit DCRO and the proposed combinational frequency multiplier in 90nm CMOS technology. The resultant frequency range is verified by simulation.

Design of novel hybrid - digitally controlled oscillator for ADPLL

Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input. But, due to practical limitations in circuit design, DCOs resolution will be highly limited. Delta Sigma Modulator (DSM) is generally used in DCOs/ADPLLs to obtain a greater resolution. However, using DSM will lead to introduction of frequency spurs in the output spectrum. In this work we propose an alternate method to increase the frequency resolution of DCO without introducing frequency spurs. Novel Hybrid DCO architecture is proposed in this work to increase the resolution. Hybrid DCO proposed in this work has both digital and analog control for tuning frequency. Digital control input of the proposed DCO provides coarse frequency control and the analog control input provides fine frequency control. It has been demonstrated in this work that by integrating Hybrid DCO and DSM with an analog low pass filter (LPF), resolution can be greatly increased, without introducing spurs in the spectrum. As a proof of concept, two Hybrid Digitally controlled Ring Oscillators (DCROs) are designed in 90 nm CMOS process, and their period Jitter performance is compared.

Analysis and design of K-band low-phase-noise differential DCOs implemented in 22 nm FD-SOI for 76–81 GHz automotive radars

This paper presents two K-band low-phase-noise digitally controlled oscillators (DCOs) with a frequency tuning range (FTR) of more than 20% for 76–81 GHz automotive radars. The proposed triple-bank DCO (T-DCO) relies on the medium-tuning and fine-tuning banks to cover the linear chirp band, thus facing the issues of complex frequency calibration and frequency overlap of more than 15% like conventional DCOs. To address these issues, an original dual-bank DCO (D-DCO) is proposed, which solely relies on the large fine-tuning bank to achieve a fine frequency resolution of 2 MHz and a fine-tuning range of 1.94 GHz by employing a customized MOM capacitor of 973 aF. Moreover, both T-DCO and D-DCO are implemented in a 22 nm FD-SOI process, achieving the best-in-class phase noise lower than −110 dBc/Hz over the entire frequency range at 1 MHz frequency offset, while consuming 24 mW from a 1.2 V supply voltage.

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power XOR-based quadrupler for clocking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of −59.7 dBc, while the measured out-of-band noise is −140.7 dBc/Hz at a 10-MHz offset.

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove the accumulated phase error of the RO, the proposed ILCM can achieve a very wide injection bandwidth, and, thus, an ultralow-jitter, even when the multiplication factor, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> , is increased above 60. To overcome the natural limitation of the PG injection, two digitally controlled oscillators (DCOs) were used to operate in a complementary manner. Since the background multi-functional calibrator (MFC) continuously synchronizes the outputs of the two DCOs, the PG-ILCM can generate a seamless output signal by combining these two signals. The proposed injection pulsewidth controller (IPWC) decreased the required delay of the digital-to-time converter (DTC), further reducing the jitter of the output signal. A phase-rotational divide-by-4 divider (PR-DIV4) also was proposed to reduce the operating frequency and the power consumption of the MFC while maintaining the fine resolution of the output frequency. The PG-ILCM, fabricated in a 65-nm CMOS process, used the power of 14.3 mW and an area of 0.102 mm2. The rms jitter measured at 8.16 GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N = 68$ </tex-math></inline-formula> ) was 97 fs.

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.

A 2 nJ/bit, 2.3% FSK Error Fully Integrated Sub-2.4 GHz Transmitter With Duty-Cycle Controlled PA for Medical Band

This paper proposed a fully integrated MBAN (2360–2400 MHz) continuous phase modulated transmitter (TX) with tunable less than 0dBm output power for medical band. A duty-cycle tuning strategy was proposed for the power amplifier (PA) featuring adaptive optimized efficiency for different output powers. A fully on-chip transformer-based match network was proposed to suppress the 2nd harmonic using a series <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO’s period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO’s stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> . The measured fundamental fractional spurs range from −56 to −45 dBc.

Systematic Design of Loop Circuit Topologies Using C/I DS Methodology

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C/I_{\text {DS}}$ </tex-math></inline-formula> methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems.

A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise

This article introduces a 28-nm CMOS digitally controlled oscillator (DCO) based on eight oscillator cores, where the number of active cores can be reconfigured to be either 2, 4, 6, or 8, trading power consumption for phase noise without incurring an additional phase noise penalty. The impact of the reconfiguration pMOS switches on the phase noise performance is determined through a simple yet rigorous time-variant circuit analysis. The octa-core DCO covers a 27% frequency tuning range between 10.7 and 14.1 GHz with an average resolution of 6 MHz. A very low phase noise level of −126 dBc/Hz is measured at 1-MHz offset from 10.7 GHz with a power consumption of 173 mW, corresponding to a phase-noise figure-of-merit of −184 dBc/Hz that remains almost constant across the tuning range.

A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From −45 °C to 85 °C

This article presents a 16-MHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> filter. Since it is made from on-chip resistors and capacitors, the filter’s characteristic is temperature dependent. To compensate for this, the control signal of the DCO is derived by digitizing the filter’s output phase and combining it with the digital output of a Wheatstone bridge temperature sensor. After a two-point trim, this digital temperature compensation scheme achieves an inaccuracy of ±90 ppm from −45 °C to 85 °C. The frequency reference draws 220 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply, with a supply sensitivity of 0.12%/V and a 320-ppb Allan Deviation floor for a 10-s stride.

A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> chirp slope, corresponding to 0.0002% of the chirp bandwidth.

A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization step of TDC is always tracked with the RO period; hence no calibration is needed in this architecture. We adopt RO tuning to lower the injection-locking bandwidth so as to decrease the power consumption of the injection current. Moreover, the fractional part of phase error detection is turned down in the coarse tuning of ADPLL to save power. An LC-based digital-controlled oscillator (LCDCO) with a 6.4 nH inductor and a resistive bias is used to have a low power and better phase noise performance. The ADPLL is fabricated in 40 nm CMOS with a 1 V supply and consumes 1.4 mW when it is locked. The measured phase noise is −114 dBc/Hz at 1 MHz offset. The test results show significant power saving. Thus, it can be a promising candidate for BLE applications.

Modification over Dithered DPLL to reduce the effect of narrowband channel interference

Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and its modified versions. To overcome the effect of channel interference, a single tone dither signal is included in the loop of DPLL. Although an improvement in acquisition and tracking performance is observed, but addition of dither signal contributes to the phase error variance and consequently output noise to increase. Therefore, a further modification is proposed by incorporating an additional phase control in the digital control oscillator (DCO) of the loop to improve the output SNR. The proposed loop is implemented on reconfigurable logic platform using System Generator, a tool from Xilinx used to design real time DSP application. The hardware simulation results demonstrate a comparison among traditional DPLL, dithered DPLL and phase controlled dithered DPLL where the proposed version of the loop outperforms others in terms of acquisition and noise rejection. Keywords DSP Digital Phase Locked Loop, Phase Controlled DPLL, Channel Interference, Dither DPLL, VHDL System Design, Modified DCO

A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS

This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10−3. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications

This article presents a 23.9–29.4 GHz digital <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .