Modification over Dithered DPLL to reduce the effect of narrowband channel interference

Abstract

Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and its modified versions. To overcome the effect of channel interference, a single tone dither signal is included in the loop of DPLL. Although an improvement in acquisition and tracking performance is observed, but addition of dither signal contributes to the phase error variance and consequently output noise to increase. Therefore, a further modification is proposed by incorporating an additional phase control in the digital control oscillator (DCO) of the loop to improve the output SNR. The proposed loop is implemented on reconfigurable logic platform using System Generator, a tool from Xilinx used to design real time DSP application. The hardware simulation results demonstrate a comparison among traditional DPLL, dithered DPLL and phase controlled dithered DPLL where the proposed version of the loop outperforms others in terms of acquisition and noise rejection. Keywords DSP Digital Phase Locked Loop, Phase Controlled DPLL, Channel Interference, Dither DPLL, VHDL System Design, Modified DCO