A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise

Abstract

This article introduces a 28-nm CMOS digitally controlled oscillator (DCO) based on eight oscillator cores, where the number of active cores can be reconfigured to be either 2, 4, 6, or 8, trading power consumption for phase noise without incurring an additional phase noise penalty. The impact of the reconfiguration pMOS switches on the phase noise performance is determined through a simple yet rigorous time-variant circuit analysis. The octa-core DCO covers a 27% frequency tuning range between 10.7 and 14.1 GHz with an average resolution of 6 MHz. A very low phase noise level of −126 dBc/Hz is measured at 1-MHz offset from 10.7 GHz with a power consumption of 173 mW, corresponding to a phase-noise figure-of-merit of −184 dBc/Hz that remains almost constant across the tuning range.