Digitally Controlled Oscillator Research Articles

A 2.4-GHz MEMS-Based PLL-Free Multi-Channel Receiver With Channel Filtering at RF

A Bulk Acoustic Wave (BAW) resonator based 2.4-GHz low power receiver is presented in this work. The intrinsic high quality factor ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> ) of the BAW resonator (around 400 at 2.4-GHz) is exploited to provide channel selection at RF and in the frequency synthesis. A novel way of addressing multiple channels (arbitrary frequency) using integer dividers and a BAW digitally controlled oscillator (DCO) and thus avoiding the need for a PLL is proposed in this work. To the best of our knowledge, this work is the first one to report a multi-channel (arbitrary frequency) receiver whose frequency synthesis depends solely on the low phase noise BAW DCO and does not include a PLL. A BAW pseudo-lattice with frequency and bandwidth tuning is proposed which significantly improves the rejection of unwanted signals in the channel filter. A quadrature sub-sampling mixer is used to down-convert the selected channel to baseband. The receiver is designed and integrated in a 0.18- μm CMOS process. With <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -boosting, the channel filter provides bandwidth down-to 1-MHz. For a BFSK modulated signal, the receiver exhibits a sensitivity of -78 \mathchar "702 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> dBm at a rate of 268-kbps for a BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . The total power consumption of the receiver is 5.94-mA from a 1.8-V power supply.

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

This paper presents a wide band, fineresolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ㎛ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ㎛ process and the die area of the solenoid inductor is 0.013 ㎟. The DCO tuning range is about 54 % at 4.1 ㎓, and the power consumption is 6.6 ㎽ from a 1.2 V supply voltage. An effective frequency resolution is 0.14 ㎑. The measured phase noise of the DCO output at 5.195 ㎓ is -110.61 ㏈c/㎐ at 1 ㎒ offset.

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9---7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm2. The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is Â?110.17 dBc/Hz at 1 MHz offset.

A wide supply voltage range and low-power all-digital clock generator

This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm2 for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm2. The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.

이진 위상-주파수 검출기와 카운터를 이용한 디지털 위상 고정 루프 회로 설계

본 논문은 이진 위상-주파수 검출기와 카운터를 사용한 새로운 위상-디지털 변환기 구조의 디지털 위상 고정 루프 회로를 제안하였다. 제안한 디지털 위상 고정 루프 회로는 위상-디지털 변환기, 디지털 루프, 디지털 제어 발진기(DCO)로 구성되어 있다. 제안된 위상-디지털 변환기 구조는 일반적인 시간-디지털 변환기(TDC)를 사용하지 않고, 이진 위상 주파수 검출기와 카운터를 사용함으로써 단순한 구조와 적은 면적으로 소비전력을 감소하는 장점을 갖는다. CMOS 0.18um 공정을 사용하여 1.0GHz에서 2.2GHz에 동작하는 디지털 위상 고정 루프 회로를 설계하였고 칩 면적은 <TEX>$0.096mm^2$</TEX>을 차지한다. 시뮬레이션 결과 전력소비는 1.65GHz 동작시 16.2mW로 나타났다. In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of <TEX>$0.096mm^2$</TEX>.

A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 800 MHz at 0.6 V, the power consumption and core area are 656 μW and 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively, in a 90-nm CMOS process.

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL.

A Low-Power DCO Using Interlaced Hysteresis Delay Cells

This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 μW at 480- and 200-MHz output, respectively.

A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL

In this work, a frequency-based model is presented to examine limit cycle and spurious behavior in a bang-bang all-digital phase locked loop (BB-ADPLL). The proposed model considers different type of nonlinearities such as quantization effects of the digital controlled oscillator (DCO), quantization effects of the bang-bang phase detector (BB-PD) in noiseless BB-ADPLLs by a proposed novel discrete-time model. In essence, the traditional phase-locked model is transformed into a frequency-locked topology equivalent to a sigma delta modulator (SDM) with a dc-input which represents frequency deviation in phase locked state. The frequency deviation must be introduced and placed correctly within the proposed model to enable the accurate prediction of limit cycles. Thanks to the SDM-like topology, traditional techniques used in the SDM nonlinear analysis such as the discrete describing function (DDF) and number theory can be applied to predict limit cycles in first and second-order BB-ADPLLs. The inherent DCO and reference phase noise can also be easily integrated into the proposed model to accurately predict their effect on the stability of the limit cycle. The results obtained from the proposed model show good agreement with time-domain simulations.

Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done.

Development of low phase noise digitally controlled CMOS ring oscillator with quadrature outputs

AbstractThis article present a development of low phase noise 14‐bit digitally controlled oscillator (DCO) based on ring oscillator with quadrature output in 0.18‐μm CMOS technology. Proposed design use digital control and feed‐forward technique to obtain wider output swing and stable quadrature output on even number of stages respectively. Designed DCO has tuning frequency range from 212 MHz to 1 GHz. Phase noise at 1‐MHz frequency offset is −123.93 dBc/Hz, which is the lowest among the recently published result. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1479–1483, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26824

Monotonic and low-power digitally controlled oscillator with portability for SoC applications

A monotonic and low-power digitally controlled oscillator (DCO) with a cell-based design for system-on-chip applications is presented. The proposed monotonic DCO not only can achieve high delay resolution and wide operation range at the same time, but also maintain the delay monotonicity. Moreover, based on the proposed varactor-interpolator fine-tuning stage, the proposed DCO can provide monotonic delay with low power consumption and low circuit complexity as compared with conventional approaches. Simulation results of the DCO show that power consumption can be improved to 0.21 mW (at 840 MHz) with 2.95 ps resolution. In addition, the proposed design can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141–1.8790 GHz with power consumption variations 251.9224–276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229–1.8868 GHz with varying power consumption of 251.9225–278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237–1.8962 GHz with power consumption of 251.928–278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

A Fast-Locking ADPLL with Time Measurable DCO

This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) for PRBS data sequences ranging from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1 to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.