Digitally Controlled Oscillator Research Articles

A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

A novel 16-bit CMOS digitally controlled oscillator (DCO) is described. This CMOS DCO design is based on a delay programmable differential latch and a novel digital control scheme which yields improved phase noise characteristics. Simulations of a 4-stage CMOS DCO using the 0.5 μm Agilent CMOS process parameters achieved a controllable frequency range of 750 MHz–1.6 GHz with a monotone tuning range of around 1 GHz. Monte Carlo simulations indicate that the time-period jitter due to random supply voltage fluctuations is under 250 ps for worst-case considerations. Also, phase noise was found to be in the range of −175 dBc at a frequency of 600 KHz from the carrier at 1.5 GHz (for digital control word of 1512 H) after numerous iterations of Monte Carlo simulations. FFT analysis indicate a total harmonic distortion (THD) of around − 57 dB for the DCO output signal. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.

A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.

A Digitally Controlled Oscillator System for SAW-Less Transmitters in Cellular Handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.

LMS-based calibration of an RF digitally controlled oscillator for mobile phones

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-μm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18--214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.

Clock recovery based on packet inter-arrival time averaging

Accurate source clock recovery is an important element of circuit emulation services (CES) over packet networks. A well-known and widely implemented technique for clock recovery in CES is the one that is based on packet inter-arrival time (sometimes called time difference of arrival (TDOA)) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has not been fully characterized analytically in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyze the effects of correlation of the PDV experienced by the constant bit rate (CBR) traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the PDV produces a large variance of the recovered clock. The paper also describes simple all-digital implementations of the clock recovery scheme using standard digitally controlled oscillators (DCOs).

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

A New Carrier Recovery Loop for High-Order Quadrature Amplitude Modulation

In this paper, we present a new all-digital carrier recovery loop for high-order quadrature amplitude modulation (QAM) signal constellations. The proposed approach is a blind phase-frequency detector structure that consists of a phase detector, a phase offset estimator, a frequency offset estimator, and a digital control oscillator. Compared to previous related approaches, the proposed algorithm provides a wider acquisition range and a more accurate estimation of frequency and phase offsets. These features are demonstrated by simulation results of the DOCSIS (Data-Over-Cable Service Interface Specifications) cable modem system.

A Low Jitter ADPLL for Mobile Applications

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 μm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

A portable digitally controlled oscillator using novel varactors

This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-/spl mu/m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.

Low-cost video decoder with 2D2L comb filter for NTSC digital TVs

A low-cost video decoder for NTSC signals is described in this paper. The proposed NTSC video decoder design employs a 2D2L comb filter, and a DDFS (direct digital frequency synthesizer)-based DCO (digital control oscillator) based on a trigonometric quadruple angle formula in a digital PLL to track and lock the demodulation clocks. The complexity of the digital video decoder is consequently drastically reduced. The overall cost of the proposed design is 7.22 mm/sup 2/ (26 K gates). The maximum power dissipation is 109.2 mW at the highest clock rate which is 21.48 MHz.

A Crystal-Based Low-Voltage All-Digital Programmable Ring Oscillator

We have designed and implemented a flexible programmable multi-channel digitally-controlled oscillator (MDCO) on an Altera MAX9400 Complex Programmable Logic Device (CPLD) chip. Based on elaborate experiments with the system, we have developed techniques by which to improve its linearity, resolution and stability in an improved MDCO design. This new architecture is programmable to oscillate from 0 Hz to a maximum that is determined by the oscillator master processing clock and the technology limitations. As crystal-based-programmable-delay cells (CBPDC) control its dominant propagation delay, the oscillator frequency thermal drift and jitter are reduced. In a complementary parallel development, to design high-speed and low-power sub-systems for high-speed applications, we have designed high-speed DCO and MDCOs by using the parameters of TSMC 0.25 um CMOS process with level 49 HSPICE models. At 3.3 Volts, the oscillation frequency has been increased up to 315 MHz in our ASIC MDCO design by using dynamic high-speed data flip-flops. In terms of specific applications, this architecture is suitable for digital wireless transceivers that use different bands for their transmit and receive modes, such as GSM and DECT. Yet to further enhance the operation of our DCOs, we have developed a new design technique by which to allow these blocks to operate at extremely low supply voltages. We have named this after IBM's work (Assaderaghi et al., IEDM Transactions, vol. 44, 414--422, March 1997) as DTMOS-like design style. Here, we use gate-bulk connected PMOS devices each in a separate Nwell to bring the PMOS-device threshold voltage further lower for operation with one Volt and below supplies. A wide-band 123 MHz, 0.6 [email protected] 1 V DCO core is designed and simulated in the same 0.25 um CMOS process.

A 0.18-/spl mu/m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

This paper describes a front-end processor for Blu-Ray Disc (BD) recorder applications. It integrates a partial response maximum likelihood (PRML) block, a data processor (DP) block, and a servo block. The PRML includes an analog-to-digital converter (ADC) and two digitally controlled oscillators (DCO) for data phase-locked loop (PLL) and wobble PLL. A nonlinear equalizer is designed to compensate for high-frequency signal components without increasing inter-symbol interference (ISI). A Teaklite DSP, an ADC, and a digital-to-analog converter are embedded for servo controls. The functions of 17PP modem and error correction code (ECC) are also implemented. Due to the proposed nonlinear equalizer in PRML, less than 2 /spl times/ 10/sup -4/ of symbol-error rate (SER), defined in the Blu-Ray Disc format book, is achieved with tangential tilt margin of /spl plusmn/0.5/spl deg/. This system on a chip (SOC) is fabricated in 0.18-/spl mu/m one-poly five-metal CMOS technology. It contains 12 million transistors in a 50-mm/sup 2/ die and consumes 0.9 W with a channel clock of 132 MHz in 2/spl times/ playback mode.

A Novel All-Digital PLL With Software Adaptive Filter

The phase-locked loop (PLL) is one of the key building blocks of modern electronic designs. This paper presents a novel PLL structure that utilizes a flying-adder frequency synthesizer as its digital control oscillator (DCO), a software implemented adaptive IIR filter as its loop filter, and a unique counter as its phase detector. This all-digital PLL (ADPLL) achieved the desired functionality with additional advantages including no off-chip R and C components required, dynamic control of the loop gain on the fly, easy implementation on the digital CMOS process. This paper presents detailed descriptions of each component of this ADPLL; it also presents the system modeling in Z-domain, by mapping from S-domain, for dynamic response, stability, and steady-state error study.

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed /spl Sigma//spl Delta/ dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is -112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below -62 dBc, while the far-out spurs are below -80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

Just-in-time gain estimation of an rf digitally-controlled oscillator for digital direct frequency modulation

A novel method of estimating gain of a digitally-controlled oscillator (DCO) for wireless RF applications is proposed and demonstrated. By executing the calculation algorithm just-in-time at the beginning of every packet, the DCO gain can be conveniently tracked and compensated. Precise and timely knowledge of the DCO gain makes possible various predictive operations of a frequency synthesizer such as the presented digital direct frequency modulation using a hybrid of predictive/closed modulation method. This enables the employment of sophisticated and fully-digital frequency synthesizers capable of compensating for analog nonidealities. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process. The presented ideas have been incorporated in a fully-compliant Bluetooth transceiver.

Time synchronization module for automatic identification system

This paper proposed a design and implementation procedure of the Time Synchronization Module (TSM) for the Automatic Identification System (AIS). The proposed TSM module uses a Temperature Compensated Crystal Oscillator (TCXO) as a local reference clock, and consists of a Digitally Controlled Oscillator (DCO), a divider, a phase discriminator, and register blocks. The TSM measures time difference between the 1 PPS from the Global Navigation Satellite System (GNSS) receiver and the generated transmitter clock. The measured time difference is compensated by controlling the DCO and the transmit clock is synchronized to the Universal Time Coordinated (UTC). The designed TSM can also be synchronized to the reference time derived from the received message. The proposed module is tested using the experimental AIS transponder set. The experimental results show that the proposed module satisfies the functional and timing specification of the AIS technical standard, ITU-R M.1371.

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.