Abstract
This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.
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