Differential Power Analysis Attacks Research Articles

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

AbstractIn this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 m2, and 74 clock cycles.

A machine learning low‐dropout regulator‐assisted differential power analysis attack countermeasure with voltage scaling

SummaryFalse key‐controlled aggressive voltage scaling (FKCAVS) technique is a lightweight and effective leakage power analysis (LPA) attack countermeasure. However, the regular FKCAVS technique may not be utilized as a countermeasure against differential power analysis (DPA) attacks unconditionally. The primary reason is that the working frequency of DPA attacks is significantly higher than the corresponding frequency of LPA attacks. Thus, it is difficult to make the speed of voltage scaling keep pace with the speed of DPA attacks by employing the regular FKCAVS technique. In this paper, a fast FKCAVS technique is proposed to maximize the security of a cryptographic circuit (CC) against DPA attacks while minimizing the corresponding overhead by embedding a machine learning low‐dropout (LDO) regulator (MLLR). As shown in the result, by deploying the proposed FKCAVS technique, the measurement‐to‐disclose (MTD) value against DPA attacks is maintained over 1 million with less than 17.4% power/area overhead.

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ∼15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ∼3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ∼4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.

Sustainable and Short-range Communication Techniques for Smart Industry Environment

The industries of the future, call for unprecedented flexibility whereas, the communication technology intervention is the best solution. For sustainable development goals in industry automation demand Dedicated Short-range Communication (DSRC) with Intelligent Transportation Systems (ITS). One of these systems' view point is the regular dissemination of safety messages. Integrating this technology with the existing Industry automation is a technical challenge. Integration also involves in imparting intelligence through digitalization of communication. With a cost of overhead power, Error Controlling Codes (ECC) provides a reliable and error-free DSRC communication system. In this paper, low power and secure digital VLSI architecture is presented to meet the sustainable integrated communication technology on chip circuitry for industry 4.0. The circuit's performance is measured in Cadence utilizing 18 nm FinFET-based ECRL adiabatic logic. The design provides maximum power savings of 99.49% over reported values for CMOS and 99.41% for pass transistor implementation. The adiabatic logic circuits constructed with ECRL are shown to have consistent peak current traces and hence can survive differential power analysis (DPA) attacks, resulting in improved circuit security.

Transparency Order and Cross-Correlation Analysis of Boolean Functions

Transparency order is considered to be a cryptographically significant property that characterizes the resistance of S-boxes in opposition to differential power analysis attacks. The S-box having low transparency order is more resistant to these attacks. Until now, little attempts have been noticed to examine theoretically the transparency order and its relationship with other cryptographic properties. All constructions associated with transparency order are relying on search algorithms. In this paper, we discuss the new interpretation of bent functions in terms of their transparency order. Using the concept of vector concatenation and correlation characteristics, we find the transparency order of Boolean functions. The notion of complementary transparency order is given. For a pair of Boolean functions, we interpret complementary transparency order by their Walsh-Hadamard transform. We establish a relationship of transparency order with cross-correlation for a pair of Boolean functions. We find a relationship of transparency order with <img src=image/13428361_01.gif>−variable decomposition bent functions. We generalize the bounds on sum-of-squares of autocorrelation in terms of transparency order of Boolean functions using Walsh-Hadamard spectra. Further the transparency order of a function fulfilling the propagation criterion about a linear subspace is evaluated.

The research of the side-channel analysis method based on deep learning for trusted platform module

At present, the trusted platform module (TPM) has been widely used in electricity, finance, transportation, and other industries, and its security has attracted much attention. The research on the side-channel attack (SCA) can be conducive to improving the security design technology of trusted platform modules. The side channel attack on the trusted platform module is studied from the initial differential power analysis (DPA) to the machine learning method. This paper introduces the deep learning techniques in SCA and proposes a new SCA technique based on deep learning. Firstly, on basis of the characteristics of SCA on TPM, we improve the convolutional neural network (CNN) models, including ResNet, VGG, and Google Net. Then, for the SM4 cipher implemented with and without countermeasures, we implement some attack experiments by exploiting the SCA based on various deep learning models and compare the experimental results with the DPA attack. The experiment results show that under the same circumstance, the SCA based on the deep learning method is more effective. We compare the effects of different CNN models and hyper-parameters to provide the basis and data for further research.

A post quantum secure construction of an authentication protocol for satellite communication

SummarySatellite's communication system is used to communicate under significant distance and circumstances where the other communication systems are not comfortable. Since all the data are exchanged over a public channel, so the security of the data is an essential component for the communicating parties. Both key exchange and authentication are two cryptographic tools to establish a secure communication between two parties. Currently, various kinds of authentication protocols are available to establish a secure network, but all of them depend on number–theoretical (discrete logarithm problem/factorization assumption) hard assumptions. Due to Shor's and Grover's computing algorithm number theoretic assumptions are breakable by quantum computers. Although Kumar and Garg have proposed a quantum attack‐resistant protocol for satellite communication, it cannot resist stolen smart card attack. We have analyzed that how Kumar and Garg is vulnerable to the stolen smart card attack using differential power analysis attack described in He et al and Chen and Chen. We have also analyzed the modified version of signal leakage attack and sometimes called improved signal leakage attack on Kumar and Garg's protocol. We have tried to construct a secure and efficient authentication protocol for satellites communication that is secure against quantum computing. This is more efficient as it requires only three messages of exchange. This paper includes security proof and performance of the proposed authentication and key agreement protocol.

Circuit-Variant Moving Target Defense for Side-Channel Attacks

The security of cryptosystems involves preventing an attacker's ability to obtain information about plaintext. Traditionally, this has been done by prioritizing secrecy of the key through complex key selection and secure key exchange. With the emergence of side-channel analysis (SCA) attacks, bits of a secret key may be derived by correlating key values with physical properties of cryptographic process execution. Information such as power consumption and electromagnetic (EM) radiation side-channel properties can be observed during encryption or decryption. These signals reflect data-dependent system behaviours that may reveal secret key information. Power and EM SCA attacks require several measurements of the target process to amplify the signal of interest, filter out noise, and derive the secret key through statistical analysis methods. Differential power and EM analysis attacks rely on correlating actual side-channel measurements to hypothetical models. The goal of this research is to increase the complexity of both power and EM SCA by introducing structural and spatial randomization of the target hardware. We propose a System-on-a-Chip (SOC) countermeasure that will periodically reconfigure an AES scheme using randomly located S-box circuit variants. We hypothesize that changing the location of the target modules between encryption runs will result in a nonconstant EM signal strength for any given point on the chip, increasing the number of traces needed to perform a localized EM SCA attack. Further, each of the S-box circuit variants will consist of functionally equivalent, structurally diverse hardware. By diversifying the implementations at the gate-level, we aim to vary the power behaviour observed by the attacker and disrupt the correlation between the hypothetical and actual power consumption, increasing the complexity of power SCA. This moving target defense aims to disrupt side-channel collection and correlation needed to successfully implement an attack.

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher

Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a significant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.

Using Genetic Algorithm in Inner Product to Resist Modular Exponentiation From Higher Order DPA Attacks

Evolutionary computation techniques have always provided fascinating results in all the fields of science and engineering. However in the area of computer security, their contribution has been comparatively very less. More specifically if we consider the side-channel attacks, use of these nature based techniques have been very nominal. Therefore, we proposed a secure protocol in this paper to combat against the Higher Order Differential Power Analysis attacks on modular exponentiation based cryptosystems using one of the popular evolutionary computation techniques. The proposed work first uses Genetic Algorithm for splitting the huge exponent within the modular exponentiation into multiple non-uniform shares. Then, this shares are randomly chosen for computing individual modular exponentiation with the help of nearest neighbor algorithm. Using Genetic Algorithm, our proposed protocol can generate reasonable number of shares which exposes secret exponent at the least. As a result, it provides significant resistance to Higher Order Differential Power Analysis attacks. Moreover, randomization in computing individual modular exponentiation secures the cryptosystem from generic power analysis attacks like SPA and DPA.

Power analysis attack resilient block cipher implementation based on 1‐of‐4 data encoding

Side-channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1-of-4 codes to resist differential power analysis attacks, which is the most investigated category of side-channel attacks. The four code words of the 1-of-4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set-0 and set-1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES-128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t-test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices

The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.

DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications

In this paper, a novel low power, adiabatic, DPA-resistant logic family based on double-gate FinFET transistors is presented. Internet-of-Things devices have gained many applications in all aspects of human life. Therefore, the security and energy efficiency of such device is very important. Radio-frequency identification tags and wireless sensor networks use AES modules to encrypt secret information. Attackers have successfully tampered these modules using differential power analysis (DPA) attacks. Therefore, DPA-resistant circuits with high immunity are desirable. The proposed logic circuit family has been simulated using HSPICE and PTM 20 nm technology parameters. Simulation results show that the proposed logic circuits consume lower power up to 40% in comparison with the previous designs. Furthermore, the security of the proposed logic is evaluated using an 8-bit SBOX as a test bench circuit. It has been shown that the proposed design is immune to a DPA, through simulated attacks using Cadence Virtuoso and MATLAB software.

A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box

In recent research, very large-scale integration (VLSI) design and its implementation plays a major role. It has been considered as compact and contains additional techniques. However, it undergoes security threats like differential power analysis (DPA) attacks, confidential information leakage, suspicious data insertion, brute force attacks, and other severe attacks. Hence, the cryptographic techniques that have been implemented to enhance the security level for VLSI devices is the focus of this survey. The symmetric cryptographic technique of advanced encryption standard (AES) is considered suitable for this security enhancement and it is an advanced encryption process, and so the intelligible data are transmitted in an unintelligible form to confuse the attackers and the data is securely transmitted without any interruption. Different techniques to implement the AES approaches in VLSI devices are analyzed. The dynamic S-box technique is also analyzed for key-dependent processes. The key-dependent S-box of block ciphers is more secure than a general fixed S-box. The strength of the cipher is increased by the usage of an S-box. A dynamic S-box, generated to be key-dependent and with a discrete logarithmic approach, enhanced the S-box nonlinearity. Several measures analyzed regarding security and complexity of nonlinear transformation of S-box improved. Hence, the AES algorithm with dynamic S-box makes the system dynamic, more nonlinear, and with an unbreakable architecture. In this review, it also identified that to implement nonlinear transformation in AES, an S-box component has been used. This survey has been provided as guidelines for VLSI architecture implementation in a more secure way with cryptographic algorithm of AES and a dynamic S-box.

JPEG Images Encryption Scheme Using Elliptic Curves and A New S-Box Generated by Chaos

This paper proposes a new symmetric encryption system based on an elliptical curve and chaos, where the encryption is done in a single block and runs for 14 rounds. Here, the 15 encryption keys have the same size as the image and are generated using a solution point of a strong elliptic curve. Using a string of random numbers obtained with a logistic map, a permutation and its inverse are generated, which improve the encryption level and add diffusion to the cryptosystem. Another important contribution to this research is the generation of a substitution box with a non-linearity of 100, which strengthens the cryptosystem against differential and linear attacks that add confusion to the scheme. Moreover, the cryptographic properties of the proposed S-Box are compared with those of the S-Box of the Advanced Encryption Standard (AES) to ascertain that it is a suitable alternative that it is resistant to differential power analysis (DPA) attacks. To verify the robustness of proposed cryptosystem against cryptanalysis and the quality of the cipher text obtained, this system is subjected to different tests, such as entropy, correlation coefficient, χ2, Changing Pixel Rate (NPCR), and Unified Averaged Changing Intensity (UACI). The results are shown and compared with recently proposed systems.

Approximate Adiabatic Logic for Low-Power and Secure Edge Computing

Approximate computing is a promising approach for error-tolerant applications running on the Internet-of-Things edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is true sum approximate adder (TSAA), whereas the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS-based accurate mirror adder (AMA). At 12.5-MHz operating frequency and 45-nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48% and energy savings of 90.80% and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks.

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems with Fast 16-bit Residue Channels

Hardware realization of public-key cryptosystems often entails Montgomery modular multiplication (MMM), which is more efficient in residue number systems (RNS). A large pool of co-prime moduli allows for higher number of dynamically changeable moduli-set pairs for the required base extension, leading to ultra-wide key-lengths to accommodate the indispensable resistance to differential power-analysis (DPA) attacks. The moduli are often of the form 2^r-, where r denotes the width of residue channels. In a previous relevant RNS MMM design, with r=64, probability of a successful DPA attack is less than 2^(-66), where efficient arithmetic is obtained only for a limited set of moduli that are insufficient for key-lengths over 1024 bits. Here we propose a free- RNS MMM scheme, for up-to 8192-bit key-lengths and fast 16-bit residue channels, based on the proposed -independent modulo-(2^r-) adders and multipliers. Moreover, we propose an especial method for moduli selection that is required for base extension, leading to the same aforementioned DPA-resistance measure and much lower measures for key-lengths over 1024. The implementation results show 82%,69%,44% less RSA delay, for key-lengths 512,1024,2048, respectively of the home designs versus the 512-bit main reference design, and more than 5%,100% for 4096,8192 key-lengths, respectively, all per 512-bit encrypted messages.

Energy Efficient Adiabatic Logic Circuit for Improve Security in DPA Resistant RFID

A Differential Power Analysis (DPA) attack is an exploit which overcomes the hardware and software security by analyzing the correlation between electricity usage of a chip in a device and the encryption key. These attacks are non-invasive, leading an intruder to crack a system without leaving any trace. CMOS Technology is prone to DPA attack because of higher power dissipation. A DPA resistant adiabatic technique has been analyzed which has lower power dissipation when compared to the CMOS technology. The conventional Positive Feedback Adiabatic Logic (PFAL) suffers from certain non-adiabatic energy loss. Hence, Energy Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) is proposed which reduces the non-uniform power consumption, preventing information leakage thus securing the system from DPA attacks. Thus the proposed EE-SPFAL is used to design logical circuits such as buffer, OR-XNOR and AND-NAND gate. It is proved that the information leakage in the form of current consumption takes place in PFAL buffer whereas current consumption traces in EE-SPFAL circuits are uniform, depicting the ability of the proposed logic family to resist DPA attack. The simulation was done using Cadence virtuoso 180 nm technologies.

Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses

Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind STTL are valid in general and particularly for FPGAs. Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential electromagnetic attacks (DEMA).