Differential Nonlinearity Error Research Articles

A high performance CMOS A/D converter for a digital camcorder system

In a digital camcorder system, an A/D converter which converts the analog CCD (charge coupled device) signal into digital codes has an important role in determining the system performance. An A/D converter which has an 8-bit resolution and a 40 MSPS conversion speed is proposed. It has a ping-pong architecture. With 0.8 /spl mu/m double poly and double metal CMOS technology, the experimental prototype of the proposed A/D converter has a /spl plusmn/0.5 LSB integral nonlinearity error (INL) and /spl plusmn/0.5 LSB differential nonlinearity error (DNL).

A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM

A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, "write once" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as /spl plusmn/1.5 LSB and differential nonlinearity errors of /spl plusmn/0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 /spl mu/m 10 V BiCMOS process and consumes 500 mW of power.

Reliability of code density test for high resolution ADCs

The effect of convertor internal noise on its output code histogram is analysed. Simulations show that large linearity errors, including missing codes, may vanish when sufficient noise is experienced. Consequently, the code density test is likely to yield a differential nonlinearity error within +/-0.5 LSB for any high accuracy noisy convertor.

A monolithic 2-b delta-sigma A/D converter

Oversampled delta-sigma converters have been used for high-resolution analog-to-digital conversion over a wide range of input frequencies. Oversampled converters reduce the need for complex antialias filters, eliminate sample-and-hold amplifiers, and are free of differential nonlinearity errors. A fourth-order converter with a dynamic range of 123 dB and a signal-to-total-harmonic-distortion ratio of 126 dB is described. The input voltage range is 20 V peak to peak, the input signal bandwidth is DC to 500 Hz, the clock frequency is 1024 MHz, and the output word rate is 32 K/s. The 4.48*6.53-mm chip is packaged in a 28-pin plastic leaded chip carrier/leadless chip carrier (PLCC/LCC) and dissipates 120 mW using +5 V, -5 V, and ground. >

逐次比較A/Dコンバータの微分非直線性誤差補正

逐次比較A/Dコンバータの微分非直線性誤差補正

A 12-bit, 1-MHz, two-step flash ADC

A monolithic 12-b 1 MHz, two-step flash analog-to-digital converter (ADC) has been implemented in standard 3- mu m CMOS technology. A 12-b accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter offset, gain, and nonlinearity errors. The converter differential nonlinearity errors below 1/2 LSB and the S/(N+D) signal to noise is 70 dB for 100-kHz analog input. >