Abstract
A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, "write once" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as /spl plusmn/1.5 LSB and differential nonlinearity errors of /spl plusmn/0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 /spl mu/m 10 V BiCMOS process and consumes 500 mW of power.
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