Differential Low Noise Amplifier Research Articles

Differential BroadBand (1-16 GHz) MMIC GaAs mHEMT Low-Noise Amplifier for Radio Astronomy Applications and Sensing.

A broadband differential-MMIC low-noise amplifier (DLNA) using metamorphic high-electron-mobility transistors of 70 nm in Gallium Arsenide (70 nm GaAs mHEMT technology) is presented. The design and results of the performance measurements of the DLNA in the frequency band from 1 to 16 GHz are shown, with a high dynamic range, and a noise figure (NF) below 1.3 dB is obtained. In this work, two low-noise amplifiers (LNAs) were designed and manufactured in the OMMIC foundry: a dual LNA, which we call balanced, and a differential LNA, which we call DLNA. However, the paper focuses primarily on DLNA because of its differential architecture. Both use a 70 nm GaAs mHEMT space-qualified technology with a cutoff frequency of 300 GHz. With a low power bias Vbias/Ibias (5 V/40.5 mA), NF < 1.07 dB "on wafer" was achieved, from 2 to 16 GHz; while with the measurements made "on jig", NF = 1.1 dB, from 1 to 10 GHz. Furthermore, it was obtained that NF < 1.5 dB, from 1 to 16 GHz, with a figure of merit equal to 145.5 GHz/mW. Finally, with the proposed topology, several LNAs were designed and manufactured, both in the OMMIC process and in other foundries with other processes, such as UMS. The experimental results showed that the NF of the DLNA MMIC with multioctave bandwidth that was built in the frequency range of the L-, S-, C-, and X-bands was satisfactory.

High Precision Ping-Pong Auto-Zeroed Lock-in Fluorescence Photometry Sensor.

This paper presents a high-precision CMOS fluorescence photometry sensor using a novel lock-in amplification scheme based on switched-biasing and ping-pong auto-zeroing techniques. The CMOS sensor includes two photodiodes and a lock-in amplifier (LIA) operating at 1 kHz. The LIA comprises a differential low-noise amplifier using a novel switched-biasing ping-pong auto-zeroed scheme, an automatic phase aligner, a programmable gain amplifier, a band-pass filter, a mixer, and an output low-pass filter. The design is fabricated in 0.18-µm CMOS process, and the measurement shows that the LIA can retrieve noisy input signals with a dynamic reserve of 42 dB, while consuming only 0.7 mW from a 1.8 V supply voltage. The measured results show that the LIA can detect a wide range of incident light power from 8 nW to 24 µW. The proposed design is encapsulated in a 3D-printed housing allowing for real-time invitro biomarker detection. This ambulatory platform uses an LED and a fiber optic to convey the excitation light to the sample and retrieve the fluorescence signal. Experiments with a beads solution diluted in PBS demonstrate that the sensor has a sensitivity of 1:100 k. Experimental results obtained invitro with NIH3T3 mouse cells tagged with membrane dye show the ability of the prototype to detect different densities of cell culture. The portable prototype, which includes optical filters and a small 30 mm × 36 mm × 30 mm printed circuit board enclosed inside the 3D-printed housing, consumes 36.7 mW and weighs 120 g.

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm.

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than -10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

Low Power RF Low Noise Amplifier Design for 5G Wi-Fi Receiver

This paper presents the design of a differential Low Noise Amplifier (LNA) for a 5th generation Wi-Fi Receiver. The circuit is implemented with 90nm transistors using CMOS technology. The proposed differential LNA for 5G Wi-Fi (IEEE 802.11ac) is designed by combining two single-ended 5G Wi-Fi LNAs with optimized design values. The gate and source degenerated inductance values are optimized to achieve a 5GHz frequency of operation. Noise neutralization capacitors of 10pF are used to reduce the channel noise in the MOSFETs used in the circuit. The differential LNA achieves 93.6% input matching, an input impedance of 45.94Ω, a transducer gain of 25.76dB, a noise figure of 1.52dB, P1dB of -11.7dBm and IIP3 of 3.17dBm. Index Terms: CMOS, Noise Figure, 1dB compression point (P1dB), Third Order Input Intercept Point (II3), harmonic signal, ISM Band

An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling

This article presents a multiband low-power and low-complexity impulse radio ultrawideband (IR-UWB) noncoherent receiver. The proposed receiver can be digitally reconfigured in three different modes of operation, including two single-band modes and one concurrent dual-band mode. In the two single-band modes, the proposed envelope detection architecture is capable of receiving and demodulating an on–off keying (OOK) pulse stream at RF center frequencies of 2.8 or 4.8 GHz. In the concurrent dual-band mode, the proposed architecture is able to demodulate binary frequency-shift keying (FSK), in addition to OOK demodulation, at center frequencies of 3 and 5 GHz. The receiver is composed of a reconfigurable low-power differential low noise amplifier (LNA), a fully differential squarer (self-mixer circuit), low-pass filter (LPF), and variable gain baseband (BB) amplifiers. The receiver is fabricated in TSMC 130-nm CMOS process technology. The receiver can operate at up to 150 Mb/s with the ternary signaling that is enabled by the binary FSK modulation combined with the OOK modulation in concurrent dual-band mode. At its maximum gain, the receiver achieves a sensitivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 72 dBm at a bit error rate (BER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-3}$</tex-math> </inline-formula> at a 100-Mb/s data rate. It consumes 11.9 and 13.2 mW from a 1.2-V supply in the single-band modes and concurrent dual-band mode, respectively.

A 0.38 V Fully Differential K-Band LNA with Transformer-Based Matching Networks

The implementation of a 0.38 V K-band low-power fully differential low-noise amplifier (LNA) in a 45 nm silicon-on-insulator (SOI) process is presented. The proposed architecture employs a two-stage approach with transformer-based interstage matching networks to minimize circuit area. The proposed LNA covers the frequency range from 20.3 to 24.1 GHz, it achieves a noise figure (NF) as low as 2.2 dB, and a gain of 12.9 dB, with a power consumption of 11.7 mW from a 0.38 V DC supply in a very compact area (0.15 mm2) excluding pads. Non-linearity simulations show the proposed circuit achieves a Po1dB of −7.3 dBm, and an OIP3 (Output Third Order Intercept) of 7 dBm. The transformers allow improved area use since they are simultaneously used as matching networks, RF chokes to bias the active devices, baluns at the input and output terminals to convert the single-ended signal into differential mode, and vice versa, and facilitates the interconnection with the upcoming stages. We used a state-of-the-art tool that generates the desired inductances to perform impedance matching for a given frequency and coupling factor value. A comparison with similar works proves the proposed LNA achieves a very low NF and the lowest power consumption reported in a differential circuit.

Frequency-Reconfigurable Dual-Band Low-Noise Amplifier With Interstage Gm-Boosting for Millimeter-Wave 5G Communication

A differential low-noise amplifier (LNA) for the 5G n257 band and a frequency reconfigurable differential LNA for both the 5G n257 and n260 bands (26.5–29.5 and 37–40 GHz), fabricated in a 65-nm CMOS process, are presented. Both LNAs achieve better gain and noise figure performances due to the use of magnetically coupled gm-boosting in the common-gate stage of a cascode amplifier. Furthermore, the frequency-reconfigurable LNA uses frequency reconfigurable matching circuits at the input, interstage, and output to achieve optimal noise and gain matchings for each band. The single band LNA has a core chip area of 0.11 mm2, a peak gain of 11.9 dB, a 3-dB bandwidth of 5.3 GHz, and a noise figure of 2.79 dB at 28.5 GHz. The dual-band LNA is capable of dual-band operation due to the reconfiguring matching circuits with switched coupled inductors (SCIs) and switched capacitors. It has a core chip area of 0.12 mm2, peak gains of 11.1/8.5 dB, 3-dB bandwidths of 4.8/9.4 GHz, and minimum noise figures of 3.49/4.01 dB at 28.5/38 GHz, respectively.

Design of a Differential Low-Noise Amplifier Using the JFET IF3602 to Improve TEM Receiver.

The observed data of transient electromagnetic (TEM) systems is often contaminated by various noises. Even after stacking averages or applying various denoising algorithms, the interference of the system noise floor cannot be eliminated fundamentally, which limits the survey capability and detection efficiency of TEM. To improve the noise performance of the TEM receiver, we have designed a low-noise amplifier using the current source long-tail differential structure and JFET IF3602 through analyzing the power spectrum characteristics of the TEM forward response. By the designed circuit structure, the JFET operating point is easy to set up. The adverse effect on the JFET differential structure by JFET performance differences is also weakened. After establishing the noise model and optimizing the parameters, the designed low-noise differential amplifier has a noise level of 0.60nV/Hz, which increases the number of effective data 2.6 times compared with the LT1028 amplifier.

Preclinical safety study of a fully implantable, sub-scalp ring electrode array for long-term EEG recordings

Objective. Long-term electroencephalogram (EEG) recordings can aid diagnosis and management of various neurological conditions such as epilepsy. In this study we characterize the safety and stability of a clinical grade ring electrode arrays by analyzing EEG recordings, fluoroscopy, and computed tomography (CT) imaging with long-term implantation and histopathological tissue response. Approach. Seven animals were chronically implanted with EEG recording array consisting of four electrode contacts. Recordings were made bilaterally using a bipolar longitudinal montage. The array was connected to a fully implantable micro-processor controlled electronic device with two low-noise differential amplifiers and a transmitter-receiver coil. An external wearable was used to power, communicate with the implant via an inductive coil, and store the data. The sub-scalp electrode arrays were made using medical grade silicone and platinum. The electrode arrays were tunneled in the subgaleal cleavage plane between the periosteum and the overlying dermis. These were implanted for 3–7 months before euthanasia and histopathological assessment. EEG and impedance were recorded throughout the study. Main results. Impedance measurements remained low throughout the study for 11 of 12 channels over the recording period ranged from 3 to 5 months. There was also a steady amplitude of slow-wave EEG and chewing artifact (noise). The post-mortem CT and histopathology showed the electrodes remained in the subgaleal plane in 6 of 7 sheep. There was minimal inflammation with a thin fibrotic capsule that ranged from 4 to 101 μm. There was a variable fibrosis in the subgaleal plane extending from 210 to 3617 μm (S3–S7) due to surgical cleavage. One sheep had an inflammatory reaction due to electrode extrusion. The passive electrode array extraction force was around 1 N. Significance. Results show sub-scalp electrode placement was safe and stable for long term implantation. This is advantageous for diagnosis and management of neurological conditions where long-term, EEG monitoring is required.

Differential Retrodirective Array With Integrated Circuits in Low-Cost 0.18 μm CMOS for Automatic Tracking

This communication presents a differential retrodirective array (RDA) for real-time tracking. The proposed differential RDA consists of three phase-conjugating chips and two circularly polarized antenna arrays. The phase-conjugating circuit chip which is in 0.18-um CMOS process, includes a differential low-noise amplifier, a double balanced mixer and a differential power amplifier. The specifically designed chip consumes 38.4 mW with a low voltage supply of 1.2 V. Experimental results of monostatic and bistatic cases show that, the RDA has a 3-dB beamwidth up to 77°. To the best knowledgement of the authors, the proposed RDA with circular polarization, which is promising for tracking free-moving targets, is the first differential RDA enabled by specifically designed low-cost CMOS chips.

A 5.8 GHz RF Receiver Front-End with 77.6 dB Dynamic Range AGC for a DSRC Transceiver

This paper presents a 5.8 GHz highly sensitive, high-dynamic-range RF receiver front-end with Automatic-Gain Control (AGC) and a high image-rejection for a Dedicated Short-Range Communication (DSRC) application. It is formed by a transceiver common matching, a single to differential Low-Noise Amplifier (LNA), an active mixer with an Image Rejection Filter, and an AGC unit. The proposed AGC unit is composed of a power-detector over the intermediate-frequency signals of the downconverter mixer. The power detector produces a wide dynamic range response signal, which eases the controllability of the AGC unit. In addition, external components are minimized, and area occupation is optimized. The proposed RF-FE is fabricated and measured in a 130-nm RF CMOS process. Experimental results show an overall dynamic range of 77.6 dB while a high sensitivity performance to an input power level of −85 dBm is measured. An overall gain of 26.4 dB for the RF-FE is obtained. The input referred P1dB is measured to be around −28.3 dBm. The 2-stage RC poly-phase filter that is applied to reject the image signal results in a maximum image rejection ratio of 39 dB.

A 2.4 GHz sub 1-mW highly linear differential LNA using balun transformer gm-boosting technique

This paper presents a passive gm-boosting differential low noise amplifier (LNA) for low power applications using a single-to-double transformer. This LNA improves noise figure and linearity with no extra power penalty by using the front-end balun together with noise and distortion cancelation. To address the excess power and noise that are introduced by the auxiliary amplifier, both the current reuse and resistive feedback techniques are used. The input balun provides the differential signals from the single ended input signal and boosts the gm of the amplifier. gm-boosting together with the distortion reduction technique improve both the second and third order nonlinearity. The detailed analysis and simulations including Gain, NF, and Linearity in a standard 65nm CMOS technology are given. Simulation results reveal that the LNA achieves over 23.5 dB gain, 2.8 dB NF, IIP3 and IIP2 of +4.3 dBm and +46 dBm, respectively. It consumes 620 µW from a 0.8 V supply voltage while the total effective die area is 0.21mm2.

A 77-GHz High Gain Low Noise Receiver for Automatic Radar Applications

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

A 0.6-V VDD W-Band Neutralized Differential Low Noise Amplifier in 28-nm Bulk CMOS

This letter presents a W-band low-power and high-gain differential low noise amplifier (LNA) fabricated in 28-nm bulk CMOS technology. This LNA operates at a 0.6-V supply voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DD</b></sub> ) to achieve low power consumption and respond to the low-voltage regime anticipated in future CMOS technology nodes. To obtain sufficient voltage headroom and mitigate the Miller effect, this LNA employs neutralized common source (CS) instead of cascode topology in each stage. The common-mode instability introduced by CS neutralization is reduced by making the secondary coil of each transformer (except the final one) center-tapped with resistors. The stability factor (K) and measure (B1) at a single-stage common mode are improved from 0.59 to 126 and from -0.14 to 0.6, respectively. In addition, each stage of this LNA uses only one transformer for conjugate matching, without any capacitor to minimize the passive loss. This LNA consists of five stages and achieves a power gain of 25 dB over 81-91 GHz (BW <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</sub> ) and a minimum noise figure (NF) of 6 dB at 85 GHz with power consumption of 15 mW and a silicon core area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Performance of ultra‐wide band DCBLNA with suspended strip line radiator for human breast cancer diagnosis medical imaging application

This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I. The performance of SSLIN is evaluated in terms of line capacitance and characteristic impedance by optimising its width. It is observed that best 50 Ωn-II. DCBLNA design-II using SSLIN have achieving a desired band of operation ranging from 1.5 to 15.7 GHz and best NF of 0.5 dB. The gain and phase imperfections are simulated to characterise balun networks. The smallest gain imperfection achieved is 0.1 dB at 10 GHz while the simulated phase imperfection turns out to be sufficiently good with 2.35° at 8 GHz. The proposed DCBLNA design-II is implemented and fabricated using RFCMOS 45 nm Taiwan Semiconductor Manufacturing Company (TSMC) process under commercial conditions. The highest figure of merit comes out to be 3.2 that ensures good accuracy of medical imaging for breast cancer diagnosis.

25–53 GHz ultra‐wideband high‐isolation passive balanced duplexer on 0.18‐ μ m BiCMOS for 5G applications

A new ultra-wideband millimetre-wave passive balanced duplexer (DUX), employing a lumped-element Wilkinson power divider and grounded-centre-tap transformer, has been developed using 0.18-m BiCMOS process for fifth generation operations at 28, 37, 39 GHz, and beyond. The developed DUX is configured single-ended transmitter (TX) and antenna (ANT) ports and differential receiver (RX) port. It has an inherent matching at TX, RX and ANT ports, high TX–RX isolation, and highly balanced differential RX waveforms, and is ready for direct integration with a differential low-noise amplifier. Analysis has been performed to confirm the DUX's characteristics and assess its performance. Measured isolation from TX to each single-ended RX port is higher than 50 and 40 dB from dc-20 GHz and dc-60 GHz, respectively. Measured insertion loss from TX to antenna is better than 6.3 dB across 13–53 GHz. Measured insertion loss from ANT to differential RX port is lower than 13.8 dB from 25 to 57 GHz with 10.8 dB at 40 GHz. The core chip only occupies 0.3 mm2.

A 22–44-GHz Phased-Array Receive Beamformer in 45-nm CMOS SOI for 5G Applications With 3–3.6-dB NF

This article presents a 22–44-GHz phased-array receive beamformer in the GlobalFoundries (GF) 45-nm CMOS SOI. The channel includes a wideband single-ended to differential low-noise amplifier (LNA), a 5-bit vector modulator (VM) phase shifter with a measured rms error of <6°, an attenuator, and a variable gain amplifier (VGA) with 16 dB of gain control. The phased-array channel results in a peak gain of 26.3 dB and a 3-dB bandwidth of 20.5–44 GHz. The measured NF is 3–3.6 dB at 22–44 GHz with an IP1dB of −27.5 to −24.5 dBm and dc power consumption of 112 mW. To the best of our knowledge, this is the first wideband phased-array beamformer that covers the entire millimeter-wave 5G band with high linearity and should be suitable for next-generation 5G systems.

Design of 130nm RFCMOS differential low noise amplifier

&lt;span&gt;In this paper, an inductively degenerated CMOS differential low noise amplifier circuit topology is presented. This low noise amplifier is intended to be used for wireless LAN application. The differential low noise amplifier proposed provide high gain, low noise and large superior out of band IIP3. The LNA is designed in 130 nm CMOS technology. Simulated results of gain and NF at 2.4GHz are 20.46 dB and 2.59 dB, respectively. While the simulated S&lt;sub&gt;11&lt;/sub&gt; and S&lt;sub&gt;22&lt;/sub&gt; are −11.18 dB and −9.49 dB, respectively. The IIP3 is −9.05 dBm. The LNA consumes 3.4 mW power from 1.2V supply. &lt;/span&gt;

An evolutionary-based design methodology for performance enhancement of a folded-cascode OTA using symbiotic organisms search algorithm and gm/ID technique

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This algorithm is quite useful in solving optimization problems but it suffers from higher computational time. Thus in order to minimize the computational time along with SOS algorithm, gm/ID design methodology is used. The proposed method not only guarantees appropriate bias conditions but also estimates the reduced search spaces for the design variables of the MOSFETs. To analyse the performance of SOS algorithm along with gm/ID design methodology, a low noise differential folded-cascode operational transconductance amplifier has been designed and verified using Cadence Spectre circuit simulator in UMC 0.18 µm CMOS process and MATLAB. From the optimisation results, it is observed that the gm/ID method combined with SOS algorithm converges earlier than SOS alone. The total computational time of simulation obtained using the proposed method is 8.59 s while errors found are less than 8%. Hence, this method not only reduces computational time but also improves the accuracy of the circuit design.

An inductorless 1.8 ​mW 2.9 ​dB NF differential LNA integrated to on-chip loop antenna with secondary loop for biomedical applications

In this paper, a fully integrated inductorless Low Noise Amplifier (LNA) and on-chip antenna for short range biomedical applications are proposed at 2.4 ​GHz. Inductorless configuration eliminates interference with on-chip antenna. A Common-Gate(CG), current re-use, capacitive cross coupled differential LNA provides low power and noise. In the proposed antenna, a secondary loop is formed by attaching the parasitic structure to the main loop antenna, which increases the radiation efficiency and gain of the antenna. The circuit is designed in UMC 65 ​nm technology. LNA and matching network are simulated using Cadence Virtuoso tool and have a gain of 22 ​dB, NF of 2.9 ​dB, IIP3 of −9.21 ​dBm, and return loss −11 ​dB at 2.4 ​GHz. From the Electromagnetic (EM) simulations using Advanced Design System (ADS), the on-chip antenna has a gain of −14dB and efficiency of 1.86%. The proposed design outperforms the state of the art LNAs integrated with on-chip antennas below 15 ​GHz by providing highest gain, lowest power consumption of 1.8 ​mW and longest computed communication range.