A 0.6-V VDD W-Band Neutralized Differential Low Noise Amplifier in 28-nm Bulk CMOS

Abstract

This letter presents a W-band low-power and high-gain differential low noise amplifier (LNA) fabricated in 28-nm bulk CMOS technology. This LNA operates at a 0.6-V supply voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DD</b></sub> ) to achieve low power consumption and respond to the low-voltage regime anticipated in future CMOS technology nodes. To obtain sufficient voltage headroom and mitigate the Miller effect, this LNA employs neutralized common source (CS) instead of cascode topology in each stage. The common-mode instability introduced by CS neutralization is reduced by making the secondary coil of each transformer (except the final one) center-tapped with resistors. The stability factor (K) and measure (B1) at a single-stage common mode are improved from 0.59 to 126 and from -0.14 to 0.6, respectively. In addition, each stage of this LNA uses only one transformer for conjugate matching, without any capacitor to minimize the passive loss. This LNA consists of five stages and achieves a power gain of 25 dB over 81-91 GHz (BW <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</sub> ) and a minimum noise figure (NF) of 6 dB at 85 GHz with power consumption of 15 mW and a silicon core area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .