Differential Cascode Research Articles

Reducing radiation-hardened DigitalCircuit power consumption

Low-power radiation-hardened sequential digital circuits supporting multiple supply voltages, integrated logic, and a low standby power state are presented. By basing the design on proven radiation hard circuits, single event effects hardness is guaranteed. The circuit is based on differential cascode voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinatorial logic supply voltage to scale for power savings. When compared to a conventional master-slave flip-flop design, the proposed flip-flop design provides up to 80% energy reduction with logic operating at reduced voltage and speed. Fifty-percent energy reduction is obtained without compromising speed when operating with all circuits at maximum voltage.

A High-Efficiency Strongly Self-Checking Asynchronous Datapath

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

A Low-Latency Asynchronous Shift Register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.

An efficient self-timed adder realized using conventional CMOS standard cells

Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 μm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.

Impact of technology scaling on CMOS logic styles

In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families namely; conventional CMOS, complementary pass logic, Domino, differential cascode voltage switch logic, and current mode logic are presented, highlighting their advantages and drawbacks. The behavior of each logic style in deep submicrometer technologies is analyzed and predicted for future technology generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8-, 0.6-, 0.35-, and 0.25-/spl mu/m CMOS technologies, and optimized for minimum energy-delay product.

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cascode voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-/spl mu/m CMOS technology, and the chip size is about 1.66 mm/spl times/1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz).

A Fine Grain Configurable Logic Block for Self‐checking FPGAs

This paper proposes a logic cell that can be used as a building block for Self‐checking FPGAs. The proposed logic cell consists of two 2‐to‐1 multiplexers, three 4‐to‐1 multiplexers and a D flip‐flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self‐checking for all single transistor stuck‐on and stuck‐off faults as well as stuck‐at faults at the inputs of each multiplexers and the D flip‐flop. The multiplexers and the D flip‐flop provide either correct (complementary) output in the absence of above‐mentioned faults; otherwise the outputs are identical.

Modular charge recycling pass transistor logic(MCRPL)

Modular charge recycling pass transistor logic (MCRPL) based on the charge recycling concept and a modular circuit design methodology is proposed for high speed and low power applications. In an 8 bit comparator, MCRPL improves the power-delay product over that obtained using dynamic differential cascode voltage switch (DCVS) logic and half-rail differential logic (HRDL) by 53 and 30%, respectively.

Active biasing of multistage CMOS op-amps for performance enhancement

The technique of active biasing is introduced and applied to a high-gain fully differential two-stage CMOS cascode op-amp, in order to enhance its various performance metrics such as gain, unity gain frequency, common mode and power supply rejection ratios, slew rate and settling time. The improved performance is predicted theoretically and substantiated through circuit simulations.

A new high performance circuit for statistical carry lookahead addition

This paper presents a new efficient VLSI implementation of a variable-time adder based on the statistical carry lookahead addition technique. As opposed to a previous proposal, the new circuit does not require precharged input signals. Therefore, it can be used in practical asynchronous system design and in mixed logic design without any auxiliary circuitry. For this reason, such implementation reduces power dissipation. The circuit is realized in domino logic and for the critical path DCVSL (differential cascode voltage switch logic) gates are used. A similar designed 56-bit adder requires 2758 transistors and shows an average delay of about 1.59ns using MOSIS 0.5μm technology.

An adiabatic differential logic for low-power digital systems

A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with refatively low gate complexity. It operates from a two-phase nonoverlapping supply clock, power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed, Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit.

Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1/f/sup /spl alpha//-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-/spl mu/m single polysilicon/double metal process, are proposed for CMOS active-pixel imagers. The first is an uncompensated switched capacitor (SC) voltage amplifier; the second, an offset compensated SC amplifier; and the third, a commutable bandpass filter. All three amplifiers allow correlated double sampling and double delta sampling for pixel and column fixed pattern noise suppression, respectively. The amplifiers offer up to 10-Mpixels/s readout rates. A detailed theoretical analysis of the amplifiers response to white noise and low-frequency excess noise is given, considering nonstationary nature of the output signals. An original method based on diffusive Markovian representation of 1/f/sup /spl alpha//-noise is used. The theoretical results are compared with experimental data.

A decision-diagram-based synthesis procedure for DCVS circuits

Differential Cascode Voltage Switch (DCVS) circuits are becoming an important emerging direction of research in the quest for high-performance CMOS integrated circuits. Potential advantages are higher circuit density and speed and lower power dissipation. In this paper we introduce a new decision-diagram-based model, the 123 decision diagram, which can be used to efficiently synthesize DCVS circuits. We compare our approach to DCVS synthesis techniques based on reduced ordered binary decision diagrams (ROBDDs) and show that our approach is guaranteed to perform as well as or better than conventional OBDD-based methods. Experiments on benchmark circuits show improvements of 0 to 48% with an average improvement of 14%.

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-/spl mu/m two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits.

Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-/spl mu/m CMOS technology with 0.25-/spl mu/m effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance.

Design Of A Cmos Carry Look-Ahead Adder For Self-Timed Circuits

This paper presents the design of a four-bit carry look-ahead adder in differential cascode voltage switch (DCVS) logic for application in self-timed circuits based on the reclusive property of the logic blocks, to extract multiple-outputs at complex gates, and on scaling techniques in the transistors. The proposed adder reduces the routing area and the number of transistors from the 256 of a conventional DCVS scheme to 190, thus producing a more compact circuit and a reduction in chip area of 30%.

Compact four bit carry look-ahead CMOS adder inmulti-output DCVS logic

A four-bit carry look-ahead (CLA) CMOS adder based on transistor sharing in a multi-output differential cascode voltage switch (MODCVS) logic is presented. This adder uses a new enhanced CLA unit, which enables the generation of all output carries in one single compact gate structure. Simulation results using HSPICE with CMOS 1.0 /spl mu/m technology designs show that the four-bit adder proposed has 15.7% less transistors, 27.2% less silicon area, /spl sim/14% speed improvement, and a 29.1% reduction in average power consumption compared to a standard DCVS implementation.

A new asynchronous pipeline scheme: application to the design of a self-timed ring divider

This paper describes an efficient means of synchronizing and pipelining asynchronous circuits implemented using differential cascode voltage switch logic (DCVSL) precharged function blocks. A modified version of this logic, called LDCVSL (latch differential cascode voltage switch logic), which is similar to the LCDL (latched CMOS differential logic), or DCVSL with NORA-latch, is used to improve the storage capability of the precharged function blocks. Improving the storage capability of the building blocks allows the design of an efficient pipeline scheme which is described in detail. Following a description of its potential performance, the pipeline scheme is applied to the design of self-timed rings. It is shown that more compact ring structures can be obtained without loss of performance. Our design methodology is then presented. It is based on the use of a private asynchronous standard cell library, fully compatible with an existing CMOS standard cell library provided by the foundry. Our approach allows the rapid design of standard cell based asynchronous circuits. Finally, both the pipeline scheme and design approach are illustrated through the design of a 32-b self-timed ring divider. The division algorithm is first briefly presented. The chip architecture is then described with the results obtained after fabrication. The test chip has been fabricated using the CNET/SGS-Thomson 0.5 /spl mu/m three metal layer technology. The 0.7 mm/sup 2/ chip computes 32-b divisions in 101 ns with a power consumption of 30 mW at a throughput of 10 million operations per second.