Differential Amplifier Research Articles

0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-Input/Output Differential Difference Transconductance Amplifiers.

This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.

A design of fully differential operational amplifier for switched-capacitor application

Switched-capacitor (SC) circuit is used widely in communication and signal processing systems, such as switched-capacitor filter and switched-capacitor integrator. This paper proposes a fully differential operational amplifier for switched-capacitor application. The designed amplifier comprises common mode feedback circuit, auxiliary amplifier and main amplifier using fold cascode structure and its biasing circuit. The supply voltage VDD is 1V and VSS is -1V. After the simulation using TSMC 0.18μm process model, the simulation result shows the proposed amplifier achieve about 100.6dB DC gain, 66 degree phase margin,333 MHz unit gain bandwidth, 3.78V differential output swing, 287V/μs slew rate,122.8 dB DC PSRR, 114 dB DC CMRR, 1.6mW power consumption, the input reference noise is about 6nV/√Hz at 1MHz, the Total Harmonic Distortion of this amplifier is less than about 1.05%.The proposed fully differential operation amplifier meet all the specification, and it can be used in some SC circuit applications.

A 77 GHz Power Amplifier with 19.1 dBm Peak Output Power in 130 nm SiGe Process.

This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70-85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-controlled base bias current source, exhibits small signal gain fluctuation of less than 5 dB and saturation output power fluctuation of less than 2 dB near the 80 GHz frequency point when the ambient temperature varies in the range of -40 °C to 125 °C. Benefiting from the aforementioned design, the tested single-path differential power amplifier exhibits a small signal gain exceeding 16 dB, a saturation output power exceeding 18 dBm, and a peak saturation output power of 19.1 dBm in the frequency band of 70-85 GHz.

Design of a 0.5 V Chopper-Stabilized Differential Difference Amplifier for Analog Signal Processing Applications.

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth.

Low-noise fast-response readout circuit to improve coincidence time resolution

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

INVESTIGATION OF THE METHOD OF AUTOMATIC COMPENSATION OF TREND COMPONENTS OF PHASE SIGNALS IN SYSTEMS OF PHASE-METRIC CONTROL OF GEODYNAMIC PROCESSES

Geodynamic monitoring is widely used to monitor and control the state of various objects, as well as to detect and evaluate their changes over time. The software and hardware systems that implement it for tracking the geodynamics of objects over long time intervals should effectively highlight the trend component in the processed data. A promising way to implement geodynamic monitoring is the use of phasemetric methods of geoelectric control. The block diagram of the phase change detection path using these methods contains a differential amplifier, a phase detector, a low-pass filter, and a highly stable reference oscillator. To eliminate an undesirable constant phase shift based on this method, it is proposed to use an automatic compensation method that allows the system phase to be adjusted automatically in real time. The result of using the auto compensator is the formation of a "new" reference signal for the phase detector, excluding the formation of these phase shifts in its output signal. To illustrate the proposed approach, the use of software implementation of automatic compensation of unwanted shifts to identify a trend in phase signals obtained during geodynamic monitoring of the near-foundation zone of a structure is considered, which has shown its effectiveness and the possibility of further practical use.

Comparative analysis of meta heuristics algorithm for differential amplifier design

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.

Fiber Optic Sensor-Based Bearing Defect Detection and Its Usages in Computer Vision

This work focuses on the investigation of surface defects in small bearings. Based on the theory of rough surface scattering and the dual-beam ratio measurement method, fiber optic sensing technology is applied in identifying surface defects in bearings. To facilitate the extraction of features for surface defects in bearings, a sensor probe fiber array with three concentric circles around the central emission is determined. A reflective intensity-modulated fiber optic sensor (FOS) is employed to detect surface defects on bearings. The structural parameters of the FOS are simulated through Matlab, considering the inner/outer diameter, numerical aperture, and axial spacing of the sensor. This work involves designing modulation light source excitation circuits, photoelectric conversion module circuits, pre-amplification differential amplifier circuits, infinite gain bandpass filtering circuits, and window function comparison circuits. This effectively amplifies the defect feature signals and eliminates noise interference. In experiments, the sensor probe is fixed on the support of a micro-displacement measurement platform. By adjusting the distance between the probe and the side surface through rotation, initial tests are conducted using standard roughness samples. The results indicate that installing the sensor probe at a distance of 0.92 mm from the side surface provides better measurement of surface roughness. The oscilloscope waveform reveals that the FOS can identify defects on different bearing surfaces. Furthermore, the bearing surface is divided into sections with engraved text (seal cover part) and without engraved text (inner and outer rings of the bearing). Using computer vision (CV) technology, a FOS detection system is designed, achieving a defect recognition rate of 99% for bearings, in line with the intended design goals.

The development of a 10.7-MHz fully balanced current-tunable bandpass filter with Caprio technique

Bandpass filters are integral in modern communication systems for selecting specific frequency ranges to ensure interference-free signal transmission and reception. This paper explores various bandpass filter designs, including those using active inductors, transmission-line unit-cells, microstrip open-loop resonators, and dual-port dual-frequency integration antennas. The focus is on the 10.7-MHz bandpass filter, widely used in FM radio and television systems. The study evaluates current-controlled and balanced designs, analyzing their performance, advantages, and drawbacks. Unique trade-offs in terms of linearity, distortion, temperature sensitivity, and component variations are discussed. Additionally, advancements in filter technology and diverse design options are presented. The paper introduces a novel current-balanced, frequency-adjusted bandpass filter to address odd-order noise issues. This filter aims to achieve high linearity, harmonic distortion attenuation, and the elimination of even-order harmonics. Through synthesis, analysis, simulation, and comparison with traditional filters, the proposed design enhances signal quality and efficiency. The fully-balanced current-tunable bandpass filter with the Caprio technique at 10.7 MHz is developed, exhibiting symmetrical characteristics with lower total harmonic distortion. The circuit’s structure is simple and adaptable for integration, validated through consistent simulation results. The study concludes by emphasizing the constant sensitivity of transistor differential amplifier circuits to the center frequency and the linear relationship between center frequency and adjustable bias current. The suggested transistor and capacitor selection criteria contribute to optimizing the circuit’s performance, aligning with the Caprio technique’s recommendations. Overall, this research presents a promising solution for achieving high-quality signal transmission in contemporary communication systems

On the Application of Thévenin Equivalent Circuits to the Analysis of Vacuum Tube Circuits

In this paper, we express Thévenin equivalent circuits seen looking into the terminals of the small-signal model of the vacuum tube triode in terms of the Thévenin equivalent circuits seen looking out of the other terminals and apply them to the analysis of the common-cathode, common-plate, and common-grid single-tube amplifier configurations, as well as a differential pair amplifier. This is an adaptation of equivalent circuit techniques for transistor circuits pioneered by Marshall Leach. The use of equivalent circuits can yield intuitive solutions that avoid solving sets of equations.

Design of a 39-GHz compact bi-directional variable gain amplifier in 65-nm CMOS

This paper presents a differential two-stage 39-GHz bi-directional variable gain amplifier (Bi-VGA) for 5G mm-Wave applications. Based on a phase compensated bi-directional structure with tail current tuning technique, a variable gain cell with small phase variation and compact area is realized. To boost the gain and ease the impedance matching, the cross-coupled transistor pairs are adopted. Analysis and simulations are undertaken to illustrate the working mechanism of accurate gain control and low phase variation. The measured Bi-VGA achieves peak gain of 15.6 dB with 3-dB bandwidth over 35–45 GHz, covering the 5G 39-GHz band (37–43.5 GHz), and a maximum OP1dB of 3.5 dBm. Fabricated in 65-nm CMOS process, the Bi-VGA consumes 67 mW from a 1.2 V power supply with a small core area of 0.46 × 0.14 mm2, and its minimum noise figure is about 6.4 dB at the maximum gain state. Across a gain tuning range of 12 dB, the phase variation is less than 6.1° over the operating frequency range.

Improvement in Sizing Constrained Analog IC via Ts-CPD Algorithm

In this work, we propose a variation of the cellular particle swarm optimization algorithm with differential evolution hybridization (CPSO-DE) to include constrained optimization, named Ts-CPD. It is implemented as a kernel of electronic design automation (EDA) tool capable of sizing circuit components considering a single-objective design with restrictions and constraints. The aim is to improve the optimization solutions in the sizing of analog circuits. To evaluate our proposal’s performance, we present the design of three analog circuits: a differential amplifier, a two-stage operational amplifier (op-amp), and a folded cascode operational transconductance amplifier. Numerical simulation results indicate that Ts-CPD can find better solutions, in terms of the design objective and the accomplishment of constraints, than those reported in previous works. The Ts-CPD implementation was performed in Matlab using Ngspice and can be found on GitHub (see Data Availability Statement).

Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

Solar Radiation Tracking Design Based on Photoelectric Sensor for Tracing Signal Reconstruction Algorithm

Due to the high precision, low power requirements, and maintenance-free nature, the four-quadrant photoelectric sensor (FQPS) and the laser displacement sensor are employed in the development of the two-axis solar tracker. Among them, when designing the optical path of the FQPS, a cavity-wandering optical path is introduced to control the spot size of the direct sunlight falling on the sensor. The sensor interface has five data transmission lines, of which four positive poles correspond to the four quadrants of the planar two-dimensional coordinate system. AD7793 is used as the signal collector and a differential amplifier with small clutter is integrated. A laser displacement sensor is installed in the solar radiation tracker to realize the self-correction of movement error. The main control circuit adopts DSP chip TMS320F28335 for the whole dual-axis sun tracker. In the experiment, Code Composer Studio was used for development, and SPA algorithm was used to measure the position. A number of error correction variables, such as year, month, day, time, minute, second, ΔT, time zone, longitude, latitude, etc., are added to the algorithm. After debugging the hardware and software, the sunrise and sunset times of a certain place on the solar terms such as spring equinox, summer solstice, autumn equinox and winter solstice in 2022 are tested, and compared with those released by the Meteorological Bureau. The tracking signal is rebuilt using proximal gradient descent technology. The results demonstrate that the signal-to-noise ratio under the reconstruction algorithm is continuously enhanced and tends to stabilize with an increase in sampling rate without noise, and it exhibits good signal reconstruction performance in the presence of noise and growing noise.

Design of Fully Differential Amplification Circuit and Analysis of Related Parameters Based on Feedback Mechanism

In this paper, a new feedback-based mismatch reduction method is proposed for CMOS process-based differential circuit design. The method combines an active feedback circuit and a differential amplifier circuit to reduce the error caused by device mismatch by utilizing the feedback signal, which is calculated to achieve higher circuit performance and accuracy. Meanwhile, based on the actual circuit simulation in Candence, it is concluded that under the conditions of input voltage of 5V, operating current of 100mA, and the same transistor parameters, the circuit with the introduction of the feedback mechanism is able to achieve a maximum gain of about 10dB and a lower common mode rejection ratio at the same frequency compared with the circuit without feedback.

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm.

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than -10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

Tunable floating and grounded memristor emulator Model

ABSTRACT A Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18m process parameter and occupies an area of 51 × 42.5 m2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Wrap-type phase unwrapping utilizing arctangent operation as a differential amplifier through shifted phase maps

This paper introduces a novel phase unwrapping algorithm based on the investigation of the arctangent function. Acting as a differential amplifier associated with nonlinear response, the arctangent operation facilitates distinguishing various wrap types. Phase jumps from two shifted-wrapped maps aligned on the same grids are combined as a pair to function as differential mode inputs. This discerns wraps from continuous and discontinuous surfaces through distinct outputs (threshold phase values). Simulations and experiments validate the feasibility of the proposed wrap-type identification. A complete mathematical form is derived to explain the effects of shifted wraps due to various causes. This paper significantly contributes to the foundational understanding of the 2π ambiguity problem in phase unwrapping.

An Investigation of the Operating Principles and Power Consumption of Digital-Based Analog Amplifiers

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.