Differential Amplifier Research Articles

A low-noise readout circuit design for multi-bit quanta image sensor

This paper presents a novel readout circuit based on low-noise charge transfer amplifier (LCTA) to suppress the readout noise in multi-bit quanta image sensor. A switched capacitor circuit is used in LCTA to reduce the kT/C noise introduced by its load capacitor, and make the noise from ADC further suppressed due to the increase of its output swing. The digital correlated double sampling of single-slope ADC is used to eliminate the fixed noise in LCTA. The low noise readout circuit is implemented by a 110 nm CMOS process. The simulation results show that the random noise of LCTA is reduced by 19% at a gain of 2 V/V compared to the conventional differential charge transfer amplifier. The increased output swing reduces the random noise power of ADC by 61%. In addition, the LCTA equivalent input fixed noise with 29.8 μVrms is eliminated. The proposed low-noise readout circuit improves the signal-to-noise ratio by 4.37 dB at small-signal conditions.

1.2 V Differential Difference Transconductance Amplifier and Its Application in Mixed-Mode Universal Filter.

This paper presents a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA). Unlike the conventional transconductance amplifier (TA), this DDTA has both advantages of the TA and the differential difference amplifier (DDA). The proposed filter can offer four-mode operations of second-order transfer functions into a single topology, namely, voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM), and transimpedance-mode (TIM) transfer functions. Each operation mode offers five standard filtering responses; therefore, at least twenty filtering transfer functions can be obtained. For the filtering transfer functions, the matching conditions for the input and passive component are absent. The natural frequency and the quality factor can be set orthogonally and electronically controlled. The performance of the proposed topology was evaluated by PSPICE simulator using the 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC). The voltage supply was 1.2 V and the power dissipation of the DDTA was 66 µW. The workability of the filter was confirmed through experimental test by DDTA-based LM13600 discrete-component integrated circuits.

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

Design of a differential power oscillator for 433 MHz WPT using e-GaN HEMTs

This paper presents a new differential power oscillator design based on a differential class-E power amplifier. The designs use high power enhancement-GaN HEMT (e-GaN) for its fast switching time, low ON resistance and wide energy band gap properties. The target application is far field wireless power transfer for wireless charging applications. The initial guess for design parameters follows the well known Sokal approach then LTSpice simulator is used to finalize the design. The simulated output power of the power oscillator is 60 W at the 433 MHz ISM band with high DC-to-RF conversion efficiency. Effect of process and design parameter variability is considered to assess the design sensitivity to manufacturing tolerances in both active and passive components.

Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial

The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.

Interference mitigation in multiuserWDM VLCsystems using differential receiver

AbstractTo eliminate the interference between wavelength division multiplexing (WDM) channels in multiuser visible light communication systems, we proposed a differential detection. Four colors laser diodes are utilized as transmitters (Txs). Three colors (channels) are used to send the data and one color is used to convey a control signal in each Tx. The control signal is applied to find the best Tx for each user and to find the level of interference of each WDM data channel. The optical receiver has six photodetectors (PDs). Three PDs receive the data and three PDs receiver control signals. Each optical receiver has three differential amplifiers. The input of each differential amplifier is the difference between the output of two PDs (one PD captures the data and interfering signals and one PD captures control signals). Thus, the amount of the interference that is calculated by the control signals of each color will be removed from each WDM data signal by the differential amplifier. Six users are assumed in our proposed system and each user is allocated one Tx. In this work, reflections up to the third order and mobility of the user are considered while using a simple wide field of view receiver.

개선된 전압 변동률을 갖는 다중 루프 저전압강하 레귤레이터

Using the 28 nm complementary metal-oxide semiconductor (CMOS) process, a multi-loop low drop-out voltage (LDO) regulator circuit was designed for use in a wireless power transmission receiver integrated circuit. The LDO regulator uses two differential error amplifiers to provide a stable output voltage to the load with a common source P-channel MOS circuit between the two amplifiers to improve the voltage variation rate (line regulation). The LDO regulator produces an output voltage of 1.2 V from an input voltage range of 1.3∽2.1 V and voltage variation rate of 5.88 mV/V. The output voltage variation rate according to the load current change (load regulation) was 3.3367 mV/mA, and a PSRR of −42 dB was obtained.

Design of an Ultra-Compact 60-GHz Bi-Directional Amplifier in 65-nm CMOS

This letter presents an ultra-compact two-stage 60-GHz differential bi-directional amplifier (DBA) design in a 65-nm CMOS process. To satisfy the stability and gain requirements, a differential neutralized bi-directional common-source gain cell combined with the cross-coupled gm-boosting technique is proposed. In addition, a layout-symmetrical coupled line transformer is used as the inter-stage matching network to achieve broadband operation, reducing insertion loss and ensuring identical responses in both forward/backward modes. The proposed DBA achieves a peak gain of 16.1 dB with a 3-dB bandwidth of 15 GHz (52-67 GHz), maximum OP <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $_{{1 ,,dB}}$ </tex> </formula> of 5.1 dBm, <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex> $P_{{SAT}}$ </tex> </formula> of 9.6 dBm, a peak PAE of 11.5% at 62 GHz, respectively, consuming 70 mW from a power supply of 1.2 V. The circuit core occupies an ultra-compact area of only 0.0675 mm².

Cascoded Active Quencher for SPADs With Bipolar Differential Amplifier in 0.35 μm BiCMOS

Fast active quenching of single-photon avalanche diodes (SPADs) is important to reduce the afterpulsing probability (APP). An option to reduce the reaction time of electronics to a SPAD's avalanche is to design a quencher exploiting bipolar transistors. A quencher in a 0.35 μm CMOS technology with a nominal supply voltage of 3.3 V, which operated with excess bias voltages up to 6.6 V, was re-designed accordingly. In the new 0.35 μm pure-silicon BiCMOS quencher, the comparator takes advantage of a bipolar differential amplifier, which additionally gives the head room to increase the width of some CMOS transistors as well. The proposed BiCMOS quencher is able to drive the load of a wire-bonded 184 μm-diameter SPAD, while the CMOS design fails. A comparison, where both chips are measured with a wire-bonded, 34 μm-diameter SPAD, shows that the BiCMOS quencher has a reaction time, which is 330 ps to 1.1 ns faster than that of the CMOS quencher.

0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator.

This paper presents the extremely low-voltage supply of the CMOS structure of a differential difference transconductance amplifier (DDTA). With a 0.3-volt supply voltage, the circuit offers rail-to-rail operational capability. The circuit is designed for low-frequency biomedical and sensor applications, and it consumes 357.4 nW of power. Based on two DDTAs and two grounded capacitors, a voltage-mode universal filter and quadrature oscillator are presented as applications. The universal filter possesses high-input impedance and electronic tuning ability of the natural frequency in the range of tens up to hundreds of Hz. The total harmonic distortion (THD) for the band-pass filter was 0.5% for 100 mVpp @ 84.47 Hz input voltage. The slight modification of the filter yields a quadrature oscillator. The condition and the frequency of oscillation are orthogonally controllable. The frequency of oscillation can also be controlled electronically. The THD for a 67 Hz oscillation frequency was around 1.2%. The circuit is designed and simulated in a Cadence environment using 130 nm CMOS technology from United Microelectronics Corporation (UMC). The simulation results confirm the performance of the designed circuits.

A Band-Pass Instrumentation Amplifier Based on a Differential Voltage Current Conveyor for Biomedical Signal Recording Applications

Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this end, a CMOS differential voltage second-generation current conveyor (DVCCII) based on a linear transconductor is presented. A new band-pass instrumentation amplifier, based on the designed DVCCII, is also implemented in this paper. The concept of the proposed differential voltage current conveyor and instrumentation amplifier is validated numerically and their predicted performance is presented. The simulation results of the presented circuits were tested for 0.18 μm TSMC CMOS technology in a post layout simulation level using the Cadence Virtuoso tool with a ±0.9 V power supply, and demonstrated that the designed DVCCII has a wide dynamic range of ±400 mV and ±0.85 mA and a power consumption of 148 μW. The layout of the DVCCII circuit occupies a total area of 0.378 μm2. It is shown that the designed DVCCII benefits from good linearity over a wide range of input signals and provides a low input impedance at terminal X. Two versions of the proposed band-pass instrumentation amplifier using pseudo resistances were designed with different specifications for two different applications, namely for EEG and ECG signals. Numerical analyses of both designs show proper outputs and frequency responses by eliminating the undesired artifact and DC component of the EEG and ECG input signals.

Single Active Element Based Electronically Controllable Capacitance Multiplier

The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ([Formula: see text] and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ([Formula: see text] and control voltage ([Formula: see text] without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18[Formula: see text][Formula: see text]m TSMC technology with [Formula: see text][Formula: see text]V power supplies. The multiplication factor is designed to be [Formula: see text] by choosing [Formula: see text][Formula: see text]V, [Formula: see text][Formula: see text][Formula: see text]A and [Formula: see text] pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91[Formula: see text]MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with [Formula: see text][Formula: see text]V power supplies. The experiment is conducted under the same multiplication factor ([Formula: see text]) as the simulation by choosing [Formula: see text] k[Formula: see text] (1% passive resistor), [Formula: see text][Formula: see text][Formula: see text]A and [Formula: see text][Formula: see text]nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1[Formula: see text]kHz–1.25[Formula: see text]MHz). By adjusting the bias current from 17.67[Formula: see text][Formula: see text]A to 400 [Formula: see text]A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39[Formula: see text][Formula: see text]A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation.

A DSP-Based EIT System With Adaptive Boundary Voltage Acquisition

Electrical Impedance Tomography (EIT), a valuable technique modality for estimating electrical properties of an object by electrode measurements. During the measurement process, high-frequency excitation signal and the large dynamic range of boundary voltage both cause negative effects on system detection accuracy. Focusing on the induced signal detection, we proposed an adaptive boundary voltage acquisition method, which thoroughly modeled the EIT system by LTSPICE and MATLAB, dynamically adjusted the boundary voltage amplitude gain according to the induced signal voltage range, and changed sampling period for high frequency component of excitation signal. A DSP-based EIT hardware experimental platform under development was constructed, including a current source integrated direct digital synthesis and data acquisition circuit. The data acquisition circuit composed of programmable differential amplifier, low-pass filter and offset adjustment circuit is used for signal acquisition. Comparative experiments are systematically implemented for evaluating the proposed method. Quantitatively, the SNR difference of each measurement channel is reduced from 26.42dB to 6.33dB. The maximum SNR of the system can reach 60.67dB. The maximum image error (IE) is reduced from 28.17% to 15.60%. Accordingly, the proposed adaptive boundary voltage acquisition method is proved to be great beneficial to improve EIT system accuracy.

Design and simulation of differential transimpedance amplifier with active feedback for optical receivers

AbstractAn active feedback network‐based bandwidth extension technique for CMOS differential transimpedance amplifier (TIA) is proposed in 0.18 µm CMOS process technology. The design consists of three stages in differential mode. The first stage is a common‐source amplifier that minimizes noise. A common collector stage is used for level shifting and buffering in the second stage. The third stage is a differential amplifier that provides additional gain. In addition to these three stages, an active CMOS negative feedback circuit is used for extending the bandwidth. The proposed design achieves a gain of 45.2 dBΩ with a 3 dB bandwidth of 21.23 GHz. The active feedback circuit provides an additional bandwidth of 7.3 GHz. The TIA achieves a data rate of 30 Gb/s with input‐referred noise current density of 63.1 pA/ and jitter of 9.07 ps. The TIA consumes a power of 10.3 mW with a supply voltage of 1.8 V.

Low-Cost High-Sensitive Plastic Optical Fiber-Based Sensor for Detection of CO(NH2)2 Urea

In this research, a urea level sensor based on plastic optical fiber was made using the macro bending method and two kinds of configurations. The sensor is made with a gamma and band configuration with a variety of cladding, no cladding, and imperfection and immersed in the urine sample which has different urea. This is aimed at determining the optimal sensor as a urea level sensor. The object measured was a urine sample with different urea concentrations ranging from 336.1 mg/dL to 1384.3 mg/dL, with the same volume for each concentration in the container or sample holder. The light from LED is transmitted through a plastic optical fiber, received by the phototransistor, then amplified by the differential amplifier, and converted by the microcontroller to voltage as the final results on the computer. Changes in urea levels result in changes in the refractive index around the sensor. The results showed that the more imperfection given to the plastic optical fiber sensor with gamma and band configuration, the better the range, sensitivity, and resolution. The best measurements were obtained in the band configuration with PANI-ZnO coating using six imperfections with the range value of 0.514 volts, the sensitivity value of 0.367 mvolt/mg dL-1, and the resolution value of 2.724 mg/dL. The sensor is suitable for urea levels in medical, agricultural, or industrial applications with the advantages of high sensitivity, low cost, and ease of operation.

Design and integrated stroke sensing of a high-response piezoelectric direct-drive valve enhanced by push-pull compliant mechanisms.

Enhancing the dynamic bandwidth of flow control valves based on piezoelectric actuators has attracted much attention in the field of precision fluid control. This paper reports a high-speed piezoelectric direct-drive flow control valve with an enhanced flow rate by introducing a new push-pull complementary compliant mechanism. An improved semi-rhombus compliant amplifying mechanism is designed to amplify the microstroke of piezo-stacks with an enhanced resonance frequency. To facilitate the design, the dynamic stiffness model of the compliant amplifying mechanism is derived and the structural parameters are optimized using the Pareto multi-objective optimization strategy. In addition, a polyvinylidene fluoride (PVDF) based high-response displacement sensor with an improved differential charge amplifier circuit is developed and integrated into the valve to measure the spool displacement in real time. A proof-of-concept prototype is fabricated, and the flow characteristics are experimentally tested in a closed-loop control with the PVDF sensor. The flow rate and dynamic bandwidth of the presented piezo-valve are evidently enhanced, reaching the dynamic bandwidth in excess of 920 Hz (-3 dB) and the flow rate of ±6 l/min (corresponding stroke is 0.2 mm) under the supply pressure of 70 bars.

High-Speed SiGe BiCMOS Detector Enabling a 28 Gbps Quasi-Coherent Optical Receiver

This brief presents a high-speed detector targeting quasi-coherent optical receivers operating up to 28 Gbps data rates. The circuit consists of a balanced rectifier based on diode-connected heterojunction bipolar transistors (HBTs) together with tailored input and output filtering networks. The rectifier is buffered by a linear DC-coupled single-ended to differential amplifier providing a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\,\Omega $ </tex-math></inline-formula> output interface. The design was fabricated in a commercial 130 nm SiGe BiCMOS technology with f textsubscript t/f textsubscript max of 250/340 GHz, and was tested on a quasi-coherent receiver setup. Optical receiver sensitivity better than −28 dBm and −26 dBm (FEC-limited BER of 1E-3) is demonstrated, respectively, at 25 and 28 Gbps data rates. To the best of the author’s knowledge, the reported circuit represents the fastest envelope detector published to date.

Impact of orientation-based solar light noise on the performance of underwater optical wireless communication system and noise cancellation

Absorption, scattering, turbulence, and ambient light affect the performance of underwater optical wireless communication (UOWC) systems. Solar light is a form of undersea ambient light that causes interference to the UOWC system severely, and various optical components have been used to suppress solar noise. Therefore, the UOWC channel realization must ensure suitable system-based parameters to offer optimal performance. However, UOWC system performance lacks verification with the system receiver (Rx) facing multiple orientations in a high intense solar light at undersea depth. This work discusses the impact of solar light on the UOWC system with its Rx facing different orientations. It is found that the Rx orientation plays a significant role in determining the system performance. Furthermore, we numerically demonstrate the cancellation of solar noise interference using back-to-back Rx with differential amplifier mechanisms and better noise cancellation for Rx horizontal orientation.

Fully Differential Miller Op-Amp with Enhanced Large- and Small-Signal Figures of Merit

A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.

Differential Retrodirective Array With Integrated Circuits in Low-Cost 0.18 μm CMOS for Automatic Tracking

This communication presents a differential retrodirective array (RDA) for real-time tracking. The proposed differential RDA consists of three phase-conjugating chips and two circularly polarized antenna arrays. The phase-conjugating circuit chip which is in 0.18-um CMOS process, includes a differential low-noise amplifier, a double balanced mixer and a differential power amplifier. The specifically designed chip consumes 38.4 mW with a low voltage supply of 1.2 V. Experimental results of monostatic and bistatic cases show that, the RDA has a 3-dB beamwidth up to 77°. To the best knowledgement of the authors, the proposed RDA with circular polarization, which is promising for tracking free-moving targets, is the first differential RDA enabled by specifically designed low-cost CMOS chips.