Differential 8T Research Articles

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

AbstractThe modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.

Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications

This paper presents a transmission-gate-based 10T (TG10T) subthreshold SRAM cell for internet of things applications. To estimate its relative strength, it is compared with six-transistor (6T), transmission gate (TG)-based 8T (TG8T), and fully differential 8T (FD8T) cells subjected to severe process variations. The simulation results are carried out using HSPICE software and a 16 nm CMOS technology node. The TG10T cell uses a differential scheme to enhance the sense margin, two TGs instead of two NMOS access transistors to enhance write-ability, and two extra buffer transistors to improve read stability. The proposed TG10T cell minimizes leakage power dissipation by means of a greater number of PMOS devices. The proposed cell shows at least a 1.67X lower read delay (T RA) and a 1.13X higher read static noise margin. In addition, it offers a 1.22X and 1.52X lower write delay (T WA), and a 1.36X and 1.40X higher write static noise margin (WSNM) than that of 6T and FD8T, respectively. The TG10T cell consumes 2.06X/1.28X lower dynamic/leakage power compared to the 6T cell. For all these improvements, it incurs a penalty of 1.24X T WA, 1.48X WSNM, and 1.12Xdynamic power when compared with the TG8T cell, at V DD = 0.36 V. However, when subjected to severe process variations, the proposed TG10T cell shows high reliability. Moreover, a 2 kb SRAM memory using the proposed TG10T cell along with peripheral circuitries is implemented to evaluate the proposed cell’s performance in an array level.

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

AbstractGraphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide‐semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single‐ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95×/3.20× and incurs a penalty of 1.16×/1.14× in read delay compared to the GNRFETs/TMDFET‐based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross‐coupled inverters pair during the write operation, enhancing write static noise margin by 1.65×/1.71×. These two TGs along with high logic level of virtual ground (VGND) control signal during hold mode reduce leakage power. Existence of a higher number of p‐type MOS (PMOS) devices, the presence of stacked transistors, and being single‐ended bitcell further reduce this metric, nearly 1.48×/1.17× designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET‐based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half‐select disturb, and therefore, bit‐interleaving architecture can be applied to reduce multi‐bit errors.

Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices

Ultra low power integrated circuits got the major attention due to its lower power dissipation in the era of Internet of Things (IoT) based smarter devices. In this context, a P-P-N based 10T SRAM cell has been designed and simulated on cadence virtuoso tool with GPDK 45nm technology node at supply voltage ranges from 0.6V to 1V. The various parameters such as static noise margin, read/write power, read/write delay of the 10T SRAM cell are determined out and compared with other considered topologies. It is interesting to notice that 10T SRAM cell shows commendable improvement in read static noise margin (RSNM) i.e. 36% and 46% as compared to conventional 6T and differential 8T SRAM cells respectively. The 10T SRAM cell also has reduction in read power of 38.52% and 38% as compared to conventional 6T and differential 8T SRAM cells respectively. The read delay of P-P-N based 10T SRAM cell is improved by 40% with compared to conventional 6T SRAM cell.

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

SummaryThis paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

Reliable write assist low power SRAM cell for wireless sensor network applications

In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Self-refreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product ( R PDP ) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product ( W PDP ) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits $1.65\times /3.03\times /1.08\times /1.38\times $ shorter write delay ( ${T} _{\text{WA}}$ ) and $3.81\times /1.20\times /1.90\times /2.13\times $ higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and $1.36\times /1.54\times /1.22\times $ shorter read delay ( ${T} _{\text{RA}}$ ) and $6.63\times $ higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes $1.05\times /1.21\times /1.10\times /1.81\times $ lower static power ( ${H} _{\text{PWR}}$ ) than that of FD8T/SEDF9T/D12T/WWL12T while showing $3.44\times $ higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes $1.01\times /1.02\times /1.04\times $ smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of $1.37\times /1.13\times $ penalty in ${T} _{\text{WA}}/{T} _{\text{RA}}$ and $6.23\times $ penalty in ${H} _{\text{PWR}}$ when compared to FD8T and BI11T, respectively, at ${V} _{\text{DD}} = \text{0.7}$ V.

A highly stable reliable SRAM cell design for low power applications

The growth in demand for power-efficient neural network accelerators has generated an intense demand for low power static random access memory (SRAM). In this context, a power-efficient transmission gate based 9-Transistor (TG9T) SRAM bitcell has been proposed in this work. In order to assess the relative performance of the proposed design in terms of major design metrics, it has been juxtaposed with contemporaneous designs such as the feedback-cutting 7T, fully differential 8T (FD8T) and single-ended disturb free 9T (SEDF9T) bitcells, while the reliability of such SRAM designs when subjected to process variations has also been analyzed. In terms of read stability (RSNM), the TG9T shows 2.87×/3.36× higher RSNM and 2.90×/2.67× narrower spread in RSNM, respectively, as compared to 7T/FD8T. In addition, it also exhibits 1.4×/6.55× higher write ability (WSNM) and 1.01×/5.05×/1.06× narrower spread in WSNM when compared with FD8T/SEDF9T and FD8T/SEDF9T/7T respectively. Moreover, a 1.15×/1.06× narrower spread in read delay (TRA) and 1.54×/1.38× narrower spread in read current (IREAD) are also exhibited by the proposed design in comparison with 7T/FD8T. The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current. Furthermore, in comparison with 7T/FD8T, TG9T consumes 2.92×/1.04× lower hold power. Additionally, the proposed cell shows 10.80×/17.81× lower write power consumption and 1.43×/18.37× lower read power consumption when compared to that of SEDF9T/FD8T and 7T/FD8T respectively. Amongst all SRAM bitcells used for comparison, the proposed bitcell yields the lowest VDD,min. The TG9T cell achieves all the aforementioned improvements at the cost of 1.22×/1.34× longer TWA and 1.93×/1.93× longer TRA when compared with 7T/SEDF9T and 7T/FD8T, respectively, at a supply voltage of 0.7 V.

Characterization of Half-Select Free Write Assist 9T SRAM Cell

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87×/3.37× higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40×/6.55× higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T,2.90×/2.67× and 1.06×/1.01×/5.05× narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11×/1.03× narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33× shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67×/0.31×/0.48× of the write power and 0.262×/0.605×/0.90× of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34×/0.96× of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62×/1.78× in write delay (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</sub> ) compared to 7T/SEDF9T and 1.58×/1.58× in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</sub> compared to 7T/FD8T cell at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 700 mV.

Design of differential TG based 8T SRAM cell for ultralow-power applications

Low power cache memory in a system on chip is in high demand today. With the lowering of MOSFET’s channel length, low-power SRAM design has become a more challenging task. This paper presents differential 8T SRAM cell with minimum power utilization. The proposed cell has one pair of transmission gate as access switches. Due to use of TG instead of pass gate access transistor its write access time (TWA) is short. The low power consumption of the cell is due to stacking effect. This paper compares design metrics of the proposed cell with conventional 6T (CON6T) and ZIGZAG 8T (ZG8T) SRAM cells. The proposed 8T SRAM cell shows 1.15×/1.17× improvement in TWA as compared to CON6T/ZG8T at a penalty of 2.65×/2× in read access time (TRA). The proposed cell consumes 3.22× less hold power compared to both CON6T and ZG8T SRAM cells. And the proposed cell consumes 4.41× (4.44×) less write power as compared to CON6T (ZG8T) SRAM cell. Our proposed cell takes 1.37× lower chip area as compared to ZG8T cell at the expense of 1.49× higher area as compared to CON6T SRAM cell. The proposed cell also achieves 1.5×/3× higher stability during write operation as compared to CON6T/ZG8T SRAM cell, respectively. Read static margin of the proposed cell is same as CON6T but 3.2× lower than ZG8T SRAM cell.

Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory

Sub-10-nm gate length devices are expected to have severe short channel effects along with new leakage mechanisms, such as direct source-to-drain tunneling (DSDT). In this paper, in order to improve the leakage and to obtain the highest performance/stability in such deeply scaled devices, we perform device–circuit cosimulation for sub-10-nm gate length to optimize devices for logic and memory. For that purpose, double-gate MOSFETs with sub-10-nm gate length are optimized using symmetric/asymmetric gate-to-source/drain underlaps to improve the ON-state current to the OFF-state current ratio and the intrinsic gate delay. Using resulting device characteristics, the effectiveness of supply gating to improve standby leakage in the circuits is studied. We show that supply gating is effective in reducing DSDT current, as well as thermionic leakage current. Also, various SRAM designs are explored to improve stability and leakage in sub-10-nm gate length bit-cells. The analysis shows that 6T SRAM bit-cells with asymmetrically underlapped devices can provide improvement in read stability over symmetric 6T bit-cells, as well as traditional 6T bit-cells. However, the need for higher stability in the sub-10-nm gate length regime due to parameter variation would require us to investigate other bit-cell configurations. Our analysis on 1R/1W differential 8T SRAM bit-cells show that significant increase in read/write stability as well as improvement in write time, and leakage can be achieved compared with the optimized 6T SRAM bit-cells.

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

Parameters Improvement for Differential SRAM Using 180 nm Technology

This paper represents a technique for a designing differential 6T SRAM with improved parameters. In SRAM designing lowering power consumption and increasing noise margin have become two essential topics in every state of art. Static RAM (SRAM) is a form of memory that holds data in the form of static. Refreshing is not requiring in the SRAM circuit. Reduction of operating voltage in SRAM degrades the stability of the cell. Our 6T SRAM is proposed design in which we have calculated Read Margin (RM), Write Margin (WM), Power consumption with temperature or without temperature. It also consumes less power when compared to the 8T SRAM design. It provides the improved write margin, read margin when compared to the other SRAM designing. The simulation has been carried out on 180 nm CMOS technology. Tanner EDA tool is used for simulation.

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

We propose a read-disturb-free, 1-read/1-write port, 8-transistor (8T) bitcell utilizing differential sensing. The conflicting design requirement of read versus write operation in a conventional 6T SRAM bitcell is eliminated using separate read/write access transistors. A distributed read-access transistor shared across the bitcells of every row enables read-disturb-free differential sensing operation with eight transistors per bitcell. Write-access transistors are upsized to form a diffusion-notch-free layout which would result in improved manufacturability. 1R/1W port nature of the proposed 8T bitcell makes it an attractive choice for the high speed, dense register file (RF) designs. Bitcell failure measurements on 20 test-chips fabricated in 90-nm CMOS technology demonstrate that the proposed differential 8T bitcell shows 220 mV lower read-Vmin, 40 mV lower hold-Vmin, 25 mV higher weak-write voltage compared to the iso-area 6T bitcell at iso-performance. At 600 mV, the proposed 8T bitcell array operates up to 67.2 MHz.

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode. Thus, several 8T and 10T cell designs have been reported, improving the cell stability. However, they either employ single-ended read port or require too large area. In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting Code (ECC). It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. To verify the technique, a 128 × 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the proposed design has 2× higher noise margin and consumes 54% less power when compared to the conventional 6T design.

Yield-Driven Near-Threshold SRAM Design

Voltage scaling is desirable in static RAM (SRAM) to reduce energy consumption. However, commercial SRAM is susceptible to functional failures when VDD is scaled down. Although several published SRAM designs scale VDD to 200-300 mV, these designs do not sufficiently consider SRAM robustness, limiting them to small arrays because of yield constraints, and may not correctly target the minimum energy operation point. We examine the effects on area and energy for the differential 6T and 8T bit cells as VDD is scaled down, and the bit cells are either sized and doped, or assisted appropriately to maintain the same yield as with full VDD. SRAM robustness is calculated using importance sampling, resulting in a seven-order run-time improvement over Monte Carlo sampling. Scaling 6T and 8T SRAM VDD down to 500 mV and scaling 8T SRAM to 300 mV results in a 50% and 83% dynamic energy reduction, respectively, with no reduction in robustness and low area overhead, but increased leakage per bit. Using this information, we calculate the supply voltage for a minimum total energy operation (VMIN) based on activity factor and find that it is significantly higher for SRAM than for logic.