Abstract
Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits $1.65\times /3.03\times /1.08\times /1.38\times $ shorter write delay ( ${T} _{\text{WA}}$ ) and $3.81\times /1.20\times /1.90\times /2.13\times $ higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and $1.36\times /1.54\times /1.22\times $ shorter read delay ( ${T} _{\text{RA}}$ ) and $6.63\times $ higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes $1.05\times /1.21\times /1.10\times /1.81\times $ lower static power ( ${H} _{\text{PWR}}$ ) than that of FD8T/SEDF9T/D12T/WWL12T while showing $3.44\times $ higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes $1.01\times /1.02\times /1.04\times $ smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of $1.37\times /1.13\times $ penalty in ${T} _{\text{WA}}/{T} _{\text{RA}}$ and $6.23\times $ penalty in ${H} _{\text{PWR}}$ when compared to FD8T and BI11T, respectively, at ${V} _{\text{DD}} = \text{0.7}$ V.
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