Dielectric Wafer Research Articles

Effect of TiO2 addition on the microstructure and electrical properties of Al2O3 ceramics

The resistivity of the dielectric layer material of a Johnsen–Rahbek (J–R) electrostatic chuck is generally between E8 and E12 Ω⋅cm, while that of pure alumina ceramic is more than E15 Ω⋅cm. Therefore, it is necessary to regulate the resistivity of the alumina ceramic for use as a dielectric layer material for a J–R-type electrostatic chuck. An electrostatic chuck requires a uniform and controllable surface temperature on the silicon wafer. Therefore, there is a certain requirement for the thermal conductivity of the dielectric layer.In this experiment, Al2O3 ceramics with different TiO2 contents (ranging from 0.08 to 3.6 wt%) were used as the research system and sintered at 1550 °C in a reducing sintering atmosphere. The obtained samples showed electrical resistivity from E9 to E14 Ω⋅cm and thermal conductivity from 26 to 37 W/m·K. The effects of Al2O3 ceramics with TiO2 on the phase composition, microstructure, relative density, electrical conductivity, and thermal conductivity were systematically studied, along with the relationship between the temperature and electrostatic adsorption force J–R and the resistivity of the sample. The addition of 1.2 wt% TiO2 gave the Al2O3 sample better overall performance; its relative density was up to 97.88 %, resistivity was reduced to 7.09 × 109 Ω cm, thermal conductivity was 27.211 W/m·K, and the electrostatic adsorption forces at 300 and 500 V/mm were up to 119 and 331 gf/cm2, respectively. The samples were primarily used as dielectric layers of the electrostatic chuck. By simulating the electrostatic adsorption between the dielectric layer and silicon wafer under an external voltage, the J–R force of stable adsorption between the electrostatic chuck and the silicon wafer was realised.

Control of ion flux-energy distribution at dielectric wafer surfaces by low frequency tailored voltage waveforms in capacitively coupled plasmas

Capacitively coupled plasmas are routinely used in an increasing number of technological applications, where a precise control of the flux and energy distribution of ions impacting boundary surfaces is required. In the presence of dielectric wafers and targets the accumulation of charges on these surfaces can significantly alter the time evolution of the sheath electric field that is accountable for ion acceleration from the plasma bulk to the surfaces and, thus, lead to parasitic distortions of process relevant ion flux-energy distributions. We apply particle in cell with Monte Carlo collisions simulations to provide insights into the operation, ion acceleration mechanisms, and the formation of such distributions at dielectric wafers for discharges in argon gas. The discharges are driven by a combination of a single high frequency (HF) (27.1 MHz) voltage signal and a low frequency (LF) (100 kHz) customized pulsed voltage waveform. The LF waveform includes a base square signal to realize narrow and controllable high energy peaks of the ion distribution, and steady-slope ramp voltage components. We discuss the distorting effect of dielectric surface charging on the ion flux-energy distribution and provide details about how the voltage ramps can restore its narrow peaked shape. The dependence of the surface charging properties on the LF pulse duty cycle and amplitude, as well as the HF voltage amplitude is revealed. The radial homogeneity of the ion flux is found to be maintained within % around the mean value for all quantities investigated. The radial electric field developing at the edge of the dielectric wafer with finite width has only a small influence on the overall homogeneity of the plasma across the whole surface, its effect remains localized to the outermost few mm of the wafer.

Adhesive Wafer Bonding Using Ultra-Thin Spray-Coated BCB Layers

Adhesive wafer bonding based on BCB bonding layers is already a proven industrial technology. Besides its material properties (optical, mechanical) interesting for various applications the use of BCB for wafer bonding is bringing significant benefits such as good adhesion (high bond strength), low thermal budget, high tolerance to substrate surface quality (microroughness, scratches, small size particles, topography) and the ability to join practically any types of materials [1].Typically the BCB bonding layers are deposited on the surface of one or both substrates using spin-coating method for a final layer thickness ranging typically between 0.5 – 1 µm and up to 50 µm [2].During the bonding process the BCB material is softening and becomes viscous: this behavior can be both useful and not useful for applications.The softening of the BCB layer during bonding allows for compensation of surface defects (surface scratches), incorporation of small particles in the layer or even embedding of significant topography in the bonding layer (electrical interconnects, patterns) [3].The main negative effect of BCB softening is revealed when the two wafers have to be precisely aligned: the compression of the soft bonding layers introduces also a shift of the two wafers, resulting in a significant misalignment budget.One way of overcoming this issue is the partial crosslinking of the BCB material prior bonding [4]: in this approach the BCB is baked additionally or UV flood exposed after the post-coating soft bake. The bond quality is similar (voids, bond strength) to the standard process but with the major benefit of totally preventing the viscous flow during bonding.In this work we report the fabrication of ultrathin BCB bonding layers ranging from 25 µm to 125 µm by spray-coating deposition. Our study is addressing some important technical and economical items related to adhesive wafer bonding using BCB layers: Technical: the use of a thin BCB layer just with soft baking will still allow for extremely low compression of the layer but with no major misalignment budget development. This way it can be used simply as a low temperature bonding layer with the advantage of maintaining the alignment accuracy.Economical: thinner layers will obviously reduce the amount of precursor material used for coating, while the use of spray coating instead of spin coating will further reduce the amount. In spray coating the layer uniformity is not reached by spin-drying (when also a loss of material occurs) but by the spray coating itself. A proprietary spray coating technology developed in house was used to deposit BCB layers on Si test wafers. This technique facilitates the precise droplet size control and therefore allows for obtaining optimized and homogenous ultra-thin layers.For BCB layers quality assessment we used Variable Angle Spectroscopic Ellipsometry (VASE) – for layer thickness and surface microroughness, Atomic Force Microscopy (AFM) – surface microroughness, layer thickness (by scratch in the layer) and Scanning Electron Microscopy (SEM) – precise layer thickness. The redundant use of the three methods is important for results confirmation as they are using significantly different dimensions range for the sampling: SEM is using nanometer range, AFM in micrometer range while VASE is working in millimeter range.In order to successfully adopt the Omnispray® technology in industrial processes the process reproducibility is a key factor. In order to study this aspect, the wafer-to-wafer as well as lot-to-lot variations were qualified in this work.Bonding quality was assessed using Scanning Acoustic Microscopy (SAM) for voids inspection. References F. Niklaus, G. Stemme, J.-Q. Lu , and R. J. Gutmann, „Adhesive wafer bonding“, J. Appl. Phys., 99, 031101 (2006)V. Dragoi, T. Glinsner, G. Mittendorfer, B. Wieder, and P. Lindner, „Adhesive wafer bonding for MEMS applications“, SPIE Proc. Vol. 5116, 160 (2003).V. Dragoi, M. Alexe, M. Hamacher, and H. Heidrich, “Microring resonators fabrication by BCB adhesive wafer bonding”, ECS Trans., 16(8), 105 (2008).F. Niklaus, R.J. Kumar, J.J. McMahon, J. Yu, T. Matthias, M. Wimplinger, P. Lindner, J.-Q. Lu, T.S. Cale, and R.J. Gutmann, “Effects of bonding process parameters on wafer-to-wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding”, MRS Proc. Vol. 863, B10.8.1 (2005).

Effect of conditioner disc wear on frictional, thermal, kinetic and pad micro-textural attributes of interlayer dielectric and tungsten chemical mechanical planarization

A brand-new conventional diamond disc was subjected to 32 h of wear during which SEM images of active diamonds were taken, and pad cut rates (PCRs) were measured. Interlayer dielectric (ILD) wafers were polished before, midway through, and after the wear test (on a brand-new pad) at several values of polishing pressure and pad-wafer sliding velocities. Tungsten wafers were also polished midway through and after the 32 h wear. Polishing was accompanied by pad surface topography analysis via confocal microscopy. The disc experienced significant diamond tip micro-wear along with dried slurry accumulation on its substrate, causing the PCR to drop by a factor of 2. Despite this drastic change, over the duration of the wear test, there were no substantial changes in pad micro-texture, nor ILD or tungsten removal rates indicating the lack of any correlation between PCR and film removal rate during the first 32 h of wear.

Investigation of Plane Defects in a Dielectric Wafer by Spectral-Domain Integral Equation Method

The spectral-domain volume integral equation is used to develop a computer model for investigating the scattering properties of plane objects in the form of elliptical cylinders embedded in a dielectric wafer. The features of the model are demonstrated for particles of different materials and different shapes.

Method of determining nondestructive pulsed laser annealing modes for dielectric and semiconductor wafers

Single-side heating of a wafer with a free surface by pulsed laser annealing has been analyzed within a quasi-static uncoupled thermoelasticity problem. An analytical relationship that can be used as a criterion of wafer thermal strength and helps to determine nondestructive modes of pulsed laser processing of dielectric and semiconductor wafers has been obtained. The model of calculation has been obtained under the assumption that the thermophysical, mechanical, and optical properties of the materials are temperatureindependent. The experimental verification of the adequacy of the model of calculation has shown quite a satisfactory agreement between the calculation and experimental data.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Method of Determining Nondestructive Pulse Laser Annealing Modes for Dielectric and Semiconductor Wafers

Single − side heating of a wafer with a free surface by pulse laser annealing has been analyzed within a quasi-static uncoupled thermal elasticity problem. An analytical relationship has been obtained that can be used as a criterion of wafer thermal stability and helps determining nondestructive modes of pulse laser processing for dielectric and semiconductor wafers. A calculation model has been obtained in the assumption of temperature-independent thermophysical, mechanical and optical properties of the materials. An experimental verification of the adequacy of the calculation model has shown quite a satisfactory agreement between the calculation and experimental data.

Evaluation of Plasma Damage to Low-k Dielectric Trench Structures by Multiple Internal Reflection Infrared Spectroscopy

Plasma etch damage is the main cause of dielectric degradation of porous low-k materials during fabrication of advanced Cu/low-k interconnects. Highly energetic ions, reactive radicals and vacuum ultraviolet radiation generated during plasma etching have been shown to break Si-CH3 bonds and form Si-OH (silanol) bonds on the top layeroforganosilicate(SiOCH)glasslow-kmaterials. 1 Thesesurfaceanchored silanol groups readily adsorb water (e ∼80) degrading the effectiveness of the low-k materials. Although electrical characterization (e.g. reliability and leakage current measurements) of fully processed interconnects can reveal dielectric degradation, these methods are costly and cannot pinpoint any particular process causing the damage. 2 Other characterization techniques can also yield information about plasma induced damage to low-k materials. 3‐6 These methods, however, are most effective for blanket wafers. Thus, there is a pressing need for a convenient metrology to identify and quantify the damage on the side walls of dielectric trench structures from plasma processing such as photoresist stripping. In this study, we utilized multiple internal reflection infrared spectroscopy (MIR-IR) to monitor water adsorption, carbon stripping and post-etch residues during the formation of trench structures in low-k dielectric materials via plasma etch and strip processes. Fourier transform infrared spectroscopy (FTIR), a fast and non-contact metrology, can provide direct observation of water adsorption and the chemical bonding structure of blanket porous low-k dielectric materials. Recently, applications of FTIR to characterize patterned dielectric wafer were reported. 7‐9 MIR-IR spectroscopy can increase detection sensitivity up to 100-fold compared with conventional FTIR because the wafer itself serves as an IR waveguide allowing for multiple detections. 10,11 In this work, a test pattern of ∼68 nm trenches with 128nmpitchwascreatedthroughoxidehardmaskplasmaetchingfollowed by organic residue stripping. Damage to the dielectric in terms of silanol formation was quantified and correlated to each plasma processing step using MIR-IR complemented by X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM).

Study on Stiffness and Conditioning Effects of CMP Pad Based on Physical Die-Level CMP Model

Chemical mechanical planarization (CMP) pad stiffness and conditioning effects were evaluated based on a physical die-level CMP model, with pad effective modulus and asperity height as parameters. In one study, patterned dielectric wafers were polished using polymeric pads of different stiffnesses. In a second study, wafers were polished by standard pads using different conditioning disks. Polishing experimental data (dielectric thickness and step height) were fitted by the physical model, enabling the extraction of the pad effective modulus and asperity height model parameters. A higher pad stiffness gives better within-die uniformity, and the conditioning disk with blocky diamonds achieves up-area only polishing for longer times. Polishing simulations using the physical model reflect a clear pattern density dependence.

Thermosonic Gold to Gold Intermetallic Advantages for CSP Packaging

Flip chip thermosonic back end assembly method is a low cost clean gold to gold interconnection method. The advancement of flip chip thermosonic process for CSP packaging of HBLED and CMOS image sensors is occurring due to the precision intermetallic clean interconnection properties and ability to provide a small form factor packaging to consumer products. This paper will investigate thermosonic metal to metal interconnection process for these high growth assembly markets. Thermosonic bonding uses a micro weld interconnection die attach method at lower bonding temperature (150°C). The thermosonic metal to metal interconnection method is lead free and the process does not use flux or solder alloys. Thermosonic flip chip die attach process uses a robust individual die “scrubbing” process which reduces assembly steps and eliminates the mass reflow oven used commonly in C4 solder process. The metal to metal interconnection method provides excellent thermal performance for HBLEDs which require the Tj peak temperature to be controlled to maximize device MTBF and overall color temperature performance. The uses of metal to metal interconnection method provide superior thermal performance when compared to solder alloys. The metal to metal interconnection method provides high precision with low particle generation for high performance bonding of CMOS image die using a low-k dielectric wafer. The line spacing for the substrate is 50 μm / 50 μm. Stud bumping machines have a ball placement accuracy of +/− 2.5 μm. Thermosonic GGI die bonders have a mounting accuracy of +/−7 μm. Thermosonic bonding has fast process bonding times of < 500 msec which is important productivity factor in cost sensitive cell phone camera and flash modules.

Vacuum-ultraviolet-induced charge depletion in plasma-charged patterned-dielectric wafers

Plasma-induced charging of patterned-dielectric structures during device fabrication can cause structural and electrical damage to devices. In this work, we report on vacuum-ultraviolet (VUV) radiation-induced charge depletion in plasma-charged patterned-silicon-oxide dielectric wafers. Charge depletion is studied as a function of photon energy and the aspect ratio of hole structures. The wafers were charged in a plasma and subsequently exposed to monochromatic-synchrotron-VUV. Surface-potential measurements after VUV exposure showed that photon energies less than 11 eV were beneficial in depleting the plasma-induced charge from the patterned-dielectric wafers. In addition, for a given photon-flux density and for photon energies less than 11 eV, VUV-induced charge depletion decreases with increasing hole aspect ratio. The results are explained with a physically plausible equivalent-circuit model, which suggests that both electron photoinjection from Si into the oxide and oxide surface conductivity play an important role in the charge-depletion process.

Non-Destructive Material Homogeneity Evaluation Using Scanning Millimeter Wave Microscopy

Millimeter wave bridge technique for non-destructive material homogeneity characterization is described. The idea of this technique is the local excitation of the millimeter waves in the testing material and the measurement of the transmitted (reflected) wave amplitude and phase in different places of it, i.e. the material plate is scanned by the beam of the millimeter waves. The results of the homogeneity measurements for dielectric wafers according to dielectric constant anisotropy are presented. The measurement technique sensitivity is discussed.

Substrate Integrated Image Guide Array Antenna for the Upper Millimeter-Wave Spectrum

A compact linear array antenna fed by substrate integrated image guide (SIIG) at 94 GHz is presented. The SIIG is a low-loss dielectric waveguide which is synthesized directly on a high dielectric constant substrate or semiconductor wafer. Such a low-cost approach of integration allows for the development of directive low profile antennas for future commercial millimeter-wave products. Special attention was directed towards the radiation elements that are fabricated in printed circuit technique on top of the SIIG. Their novel design provides a wide tuning range for the radiation coefficient and excellent linear polarization purity. In addition, an optimized reflection compensation technique effectively reduces the overall return loss and permits frequency scanning through broadside direction without suffering from a stop band due to distributed Bragg reflection. Published theory concerning the scan range of this class of frequency-scannable array antennas is extended in this work. Detailed design guidelines are given along with simulation and measurement results of a prototype. The 2 cm long implementation produced a fan beam with 11 dB gain.

Development of BaTiO<sub>3</sub> Based X7R Wafers for Single-Layer Capacitors

Research on the development and characterization of X7R BaTiO3 dielectric wafers for high frequency single-layer capacitors has been carried out. Commercial BaTiO3 powders were processed and optimized in dielectric constant (er), dissipation factor (DF) and temperature coefficient of capacitance (TCC). The results indicate a strong effect of sintering temperature on dielectric properties as well as on mechanical properties of the BaTiO3. It has been shown that the highest dielectric constant is achieved at high sintering temperatures (>1400°C) and lowest TCC at lower sintering temperatures (<1300°C). By optimizing fabrication process e.g. dry pressing, cold isostatic pressing, sintering, and machining such as grinding and lapping, BaTiO3 wafers of dielectric constant from 3400 to 3600, with a diameter approximately 50mm and thickness 150µm, have been manufactured successfully. The fabricated thin wafers exhibit the X7R capacitor characteristics of the dissipation factor (<3%) and temperature coefficient of capacitance (<±15%) in the temperature range of –55°C to 125°C.

Total reflection X-ray fluorescence spectrometry for the introduction of novel materials in clean-room production environments

In this paper, a number of case studies on the analysis of novel metallic contaminants on conventional and alternative substrates using the technique of total reflection X-ray fluorescence spectrometry (TXRF) is presented. Investigated materials include Si and Ge substrates, high-/spl kappa/ dielectric contaminants, and layers, and Si wafers contaminated with elements from metal gates and Cu interconnects. One focus is on the application and optimization of detection limits in direct TXRF. For the TXRF analysis of contaminants on Si wafers, a general conclusion is that a combination of three excitation sources is needed to cover the whole range of interest: a low-energy excitation (about 5 keV, e.g., WM/spl alpha/, Cr K/spl alpha/) for the low Z elements such as Na, Mg, and Al, a moderate-energy excitation (10-20 keV, e.g., WL/spl beta/, MoK/spl alpha/) for the 3d-transition elements, and a high-energy excitation (25-35 keV, e.g., W, continuum) for the analysis of elements such as Zr, Ru, Mo, and Pd. Also, for the analysis of novel substrates using direct TXRF, a careful selection of the excitation source results in better detection limits. In this way, detection limits at 10/sup 10/-10/sup 11/ at/cm/sup 2/ can be achieved, even for novel contaminants and substrates. As the International Technology Roadmap for Semiconductors (ITRS) requires control below 5/spl times/10/sup 9/ at/cm/sup 2/, the application of a preconcentration procedure such as vapor phase decomposition-droplet collection TXRF (VPD-DC-TXRF) is required. Proper use of this procedure allows the improvement of the detection limits by two to three orders of magnitude, depending on wafer size and chemical collection efficiency. The usability of this preconcentration procedure in combination with TXRF will be demonstrated for noble elements and germanium substrates.

Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

AbstractWafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

Sensitivity of Homogeneity Mapping of Dielectric Wafer Using Millimeter Waves

A plane electromagnetic wave normally falling on a surface of a dielectric plate has been considered to investigate the sensitivity of the dielectric constant homogeneity mapping in the dielectric wafer by measuring the phase and/or the amplitude of the millimeter wave reflected from or transmitted through it. Measurement conditions at which the highest sensitivity might be achieved are established. The sensitivity at Fabry-Perot resonance conditions as well as at frequency shifted from resonance has been considered.

Estimation of the influence of finite dielectric substrates on the far-field pattern of an array of metallic scatterers in the infrared

The far-field scattered in the infrared by an arrangement of metallic structures deposited on a dielectric wafer is estimated in this paper. The scattering is modelled by using operators that describe the far field obtained under the regime applicable for the Babinet's principle in its vectorial approach and the Stratton–Chu approximation. The far-field scattered by an arrangement of thin gold layers over a dielectric wafer under infrared illumination is computed. The model assumes a normally incident vectorial Gaussian beam focused over the arrangement plane. An angular spectrum decomposition of the field is done. Then, every plane wave is scattered by the whole structure: arrangement + substrate layer. The reflexions in the substrate layer and the arrangement action have been taken into account in an operator formalism. Numerical results estimating the influence of substrate thickness on the pattern are obtained.

Effects of the TaN x interface layer on doped tantalum oxide high- k films

A 5 Å tantalum nitride (TaN x ) thin film was deposited between the Hf- or Zr-doped TaO x high dielectric constant (high- k) film and silicon wafer to hinder the formation of the SiO x interface layer during the subsequent high-temperature annealing step. This interface contributes to the lower leakage current density, higher dielectric constant, and larger charge trapping. The improvement is attributed to the formation of the TaO x N y interfacial layer, which was confirmed by secondary ion mass spectroscopy and X-ray photoelectron spectroscopy.